default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDASYNC 1994: Salt Lake City, UT, USA
- Proceedings of the International Symposium on Advanced Research in Asynchronous Circuits and Systems, ASYNC 1994, Salt Lake City, UT, USA, November 3-5, 1994. IEEE 1994, ISBN 0-8186-6210-7
- Henrik Hulgaard, Steven M. Burns:
Bounded delay timing analysis of a class of CSP programs with choice. 2-11 - Aaron Ashkinazy, David A. Edwards, Craig Farnsworth, Gary Gendel, Shiv S. Sikand:
Tools for validating asynchronous digital circuits. 12-21 - Masashi Kuwako, Takashi Nanya:
Timing-reliability evaluation of asynchronous circuits based on different delay models. 22-31 - Peter A. Beerel, Jerry R. Burch, Teresa H.-Y. Meng:
Sufficient conditions for correct gate-level speed-independent circuits. 33-43 - Michael Kishinevsky, Jørgen Staunstrup:
Characterizing speed-independence of high-level designs. 44-53 - Geoffrey Brown, Wayne Luk, John O'Leary:
Retargeting a hardware compiler proof using protocol converters. 54-63 - Alex Kondratyev, Alexander Taubin:
Verification of the speed-independent circuits by STG unfoldings. 64-75 - Mark R. Greenstreet, Peter Cahoon:
How fast will the flip flop? 77-86 - Jakov N. Seizovic:
Pipeline synchronization. 87-96 - Edwin G. Y. Chung, Lindsay Kleeman:
Metastable-robust self-timed circuit synthesis from live safe simple signal transition graphs. 97-105 - Jordi Cortadella, Luciano Lavagno, Peter Vanbekbergen, Alex Yakovlev:
Designing asynchronous circuits from behavioural specifications with internal conflicts. 106-115 - Mark A. Franklin, Tienyo Pan:
Performance comparison of asynchronous adders. 117-125 - Uri Cummings, Andrew Lines, Alain J. Martin:
An asynchronous pipelined lattice structure filter. 126-133 - Per Torstein Røine:
Building fast bundled data circuits with a specialized standard cell library. 134-143 - Shannon V. Morton, Sam S. Appleton, Michael J. Liebelt
:
An event controlled reconfigurable multi-chip FFT. 144-153 - John F. Chappel, Safwat G. Zaky:
A delay-controlled phase-locked loop to reduce timing errors in synchronous/asynchronous communication links. 156-165 - Prabhakar Kudva, Venkatesh Akella:
A technique for estimating power in asynchronous circuits. 166-175 - José A. Tierno, Alain J. Martin:
Low-energy asynchronous memory design. 176-185 - Craig Farnsworth, David A. Edwards, Shiv S. Sikand:
Utilising dynamic logic for low power consumption in asynchronous circuits. 186-194 - Priyadarsan Patra, Donald S. Fussell:
Efficient building blocks for delay insensitive circuits. 196-205 - Mark B. Josephs, Paul G. Lucassen, Jan Tijmen Udding, Tom Verhoeff:
Formal design of an asynchronous DSP counterflow pipeline: a case study in handshake algebra. 206-215 - Mark Bickford:
Composable specifications for asynchronous systems using UNITY. 216-227 - Igor Benko, Jo C. Ebergen:
Delay-insensitive solutions to the committee problem. 228-237 - Ajay Khoche, Erik Brunvand:
Testing micropipelines. 239-246 - Marly Roncken:
Partial scan test for asynchronous circuits illustrated on a DCC error corrector. 247-256
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-12-09 23:24 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
