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ORCID20th ASYNC 2014: Potsdam, Germany
- 20th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2014, Potsdam, Germany, May 12-14, 2014. IEEE Computer Society 2014, ISBN 978-1-4799-3789-9
- Naoya Onizawa, Shoun Matsunaga, Takahiro Hanyu:
A Compact Soft-Error Tolerant Asynchronous TCAM Based on a Transistor/Magnetic-Tunnel-Junction Hybrid Dual-Rail Word Structure. 1-8 - Guangda Zhang, Wei Song
, Jim D. Garside, Javier Navaridas, Zhiying Wang:
An Asynchronous SDM Network-on-Chip Tolerating Permanent Faults. 9-16 - Danil Sokolov, Alex Yakovlev:
GALS Partitioning by Behavioural Decoupling Expressed in Petri Nets. 17-26 - Graham M. Birtwistle, Kenneth S. Stevens:
Modelling Mixed 4phase Pipelines: Structures and Patterns. 27-36 - Joycee Mekie:
Effect of Dynamic Frequency Scaling on Interface Design for Rationally-Related Multi-clocked Systems. 37-44 - Evangelia Kasapaki, Jens Sparsø:
Argo: A Time-Elastic Time-Division-Multiplexed NOC Using Asynchronous Routers. 45-52 - Matheus T. Moreira, Augusto Neutzling, Mayler G. A. Martins, André Inácio Reis, Renato P. Ribas, Ney Calazans:
Semi-custom NCL Design with Commercial EDA Frameworks: Is it Possible? 53-60 - Fu-Chiung Cheng, Yuan-Feng Chen, Shu-Chuan Huang, Ching-Yang Huang:
Synthesis of QDI FSMs from Synchronous Specifications. 61-68 - Mehrdad Najibi, Peter A. Beerel:
Integrated Fanout Optimization and Slack Matching of Asynchronous Circuits. 69-76 - Arash Saifhashemi, Hsin-Ho Huang, Peter A. Beerel:
Reconditioning: Automatic Power Optimization of QDI Circuits. 77-84 - Benjamin Z. Tang, Sunil A. Bhave, Rajit Manohar:
Low Power Asynchronous VLSI with NEM Relays. 85-92 - Matheus Trevisan Moreira, Michel Evandro Arendt, Ricardo Aquino Guazzelli, Ney Laert Vilar Calazans:
A New CMOS Topology for Low-Voltage Null Convention Logic Gates Design. 93-100 - Salomon Beer, Marco Cannizzaro, Jordi Cortadella, Ran Ginosar, Luciano Lavagno:
Metastability in Better-Than-Worst-Case Designs. 101-102 - Mike Davies, Andrew Lines, Jon Dama, Alain Gravel, Robert Southworth, Georgios D. Dimou, Peter A. Beerel:
A 72-Port 10G Ethernet Switch/Router Using Quasi-Delay-Insensitive Asynchronous Design. 103-104 - Gang Wang, Xu Wang, Xinke Chen, Shuangbai Xue:
Test and Repair Flow for Shared BISR in Asynchronous Multi-processors. 105-107 - Marc Renaudin, Aurélien Buhrig, Charles Guillemet, Robin Wilson, Sylvain Engels:
Clockless Design Performance Monitoring for Nanometer Technologies. 108-109 - Arash Saifhashemi, Dylan Hand, Peter A. Beerel, William Koven, Hong Wang:
Performance and Area Optimization of a Bundled-Data Intel Processor through Resynthesis. 110-111
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