default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID15th DAC 1978: Las Vegas, Nevada, USA
- Stephen A. Szygenda:
Proceedings of the 15th Design Automation Conference, DAC '78, Las Vegas, Nevada, USA, June 19-21, 1978. ACM 1978 - Hedayat Markus Bayegan, Einar J. Aas:
An integrated system for interactive editing of schematics, logic simulation and PCB layout design. 1-8 - Adrian Baer:
Maintaining integrity in complex shape definitions. 9-15 - Ratilal R. Shah, G. Y. Yan:
A practical technique for benefit-cost analysis of Computer-Aided Design and Drafting Systems. - H. T. Olson:
"A user's experience in Computer Aided Manufacturing" or "CAM" at GTE - Automatic Electric. 23-25 - Ralph J. Moses:
Distributed processing in manufacturing at GTE Automatic Electric. 26-33 - A. V. Bennettson:
Computer aids systems map-based record systems. 34-47 - Bernard Schechter:
Data preparation and entry for computer-aided mapping. 48-52 - William L. Bathke:
CAMRAS: Computer Assisted Mapping & Records Activity Systems. 53 - Arthur G. Gross:
File format for data exchange between graphic data bases. 54-59 - Ikuo Nishioka, Takuji Kurimoto, Seiji Yamamoto, Isao Shirakawa, Hiroshi Ozaki:
An approach to gate assignment and module placement for printed wiring boards. 60-69 - Leah Mory-Rauch:
Pin assignment on a printed circuit board. 70-73 - Kim R. Stevens, William M. van Cleemput, Tom C. Bennett, Jon A. Hupp:
Implementation of an interactive printed circuit design system. 74-81 - Robert S. Fisher:
A multi-pass, multi-algorithm approach to PCB routing. 82-91 - Michel T. Doreau, Luther C. Abel:
A topologically based non-minimum distance routing algorithm. 92-99 - Jirí Soukup:
Fast maze router. 100-102 - Gary H. Stange:
A test methodology for large logic networks. 103-109 - Frank C. Hsu, Peter Solecky, Lubomyr M. Zobniw:
Selective controllability: A proposal for testing and diagnosis. 110-116 - Michael A. Gianfagna:
A unified approach to test data analysis. 117-124 - Chris I. Yessios:
A notation and system for 3-D constructions. 125-132 - Harvey C. Allison, Donald P. Greenberg:
The three-dimensional graphical input method for architecture. 133-137 - Ulrich Flemming:
Representation and generation of rectangular dissections. 138-144 - Gilles Fortin:
BUBBLE: Relationship diagrams using iterative vector approximation. 145-151 - Julia Ruch:
Interactive space layout: A graph theoretical approach. 152-157 - K. S. Andonian, S. Toida:
Multisource illumination & shadowing. 158-163 - Robert W. Dvorak:
An experiment in architectural instruction. 164-166 - Ietoshi Kawano, Hiroshi Fukushima, Takeshi Numata:
The design of a data base organization for an electronic equipment DA system. 167-175 - Claude Frasson:
Generalized translation in a data base system. 176-181 - Beatriz Infante, Diane Bracken, Bill McCalla, Sam Yamakoshi, Ellis Cohen:
An Interactive Graphics System for the design of integrated circuits. 182-187 - Douglas G. Fairbairn, James A. Rowson:
ICARUS: An interactive integrated circuit layout program. 188-192 - Robert P. Larsen:
Versatile mask generation techniques for custom microelectronic devices. 193-198 - Neil Weste:
A color graphics system for I.C. mask design and analysis. 199-205 - Bryan Preas, Charles W. Gwyn:
Methods for hierarchical automatic layout of custom LSI circuit masks. 206-212 - Louis J. Hafer, Alice C. Parker:
Register-transfer level digital design automation: The allocation process. 213-219 - Edward A. Snow, Daniel P. Siewiorek, Donald E. Thomas:
A technology-relative computer-aided design system: Abstract representations, transformations, and design tradeoffs. 220-226 - Alan A. Ross, Herschel H. Loomis Jr.:
Computer aided design of microprocessor-based systems. 227-230 - A. Frederick Rosene:
Phoenix system overview. 231 - John Roder:
Phoenix architecture. 232 - Dale Smith:
Programmers workbench, unix and documentation. 233 - Alexander G. Fraser:
Circuit design aids on unix. 234 - David V. Moffat:
FORMPLOT - a forms design system. 235-239 - Yacoub M. El-Ziq:
Logic design automation of MOS combinational networks with fan-in, fan-out constraints. 240-249 - Shunichiro Nakamura, Shinichi Murai, Chiyoji Tanaka, Masayuki Terai, Hideo Fujiwara, Kozo Kinoshita:
LORES - Logic Reorganization System. 250-260 - Andreas von Bechtolsheim:
Interactive specification of structured designs. 261-263 - Marvin A. Wold:
Design verification and performance analysis. 264-270 - Thomas M. McWilliams, Lawrence C. Widdoes Jr.:
SCALD: Structured Computer-Aided Logic Design. 271-277 - Thomas M. McWilliams, Lawrence C. Widdoes Jr.:
The SCALD physical design subsystem. 278-284 - Philip S. Wilcox, H. Rombeek, D. M. Caughey:
Design rule verification based on one dimensional scans. 285-289 - Belur V. Dasarathy:
Automated techniques for product-grading systems design. 290-296 - William Fetter:
A computer graphic human figure system applicable to kineseology. 297 - Murray J. Haims:
On the optimum two-dimensional allocation problem. 298-304 - Tilak Agerwala, Yong-Chai Choed-Amphai:
A synthesis rule for concurrent systems. 305-311 - Ben Huey:
Guiding sensitization searches using problem reduction graphs. 312-320 - Bertrand T. David, G. Vitry:
SIGMA-CAD: Some new concepts in design of general purpose CAD systems. 321-325 - Charles W. Cha:
A testing strategy for PLAs. 326-334 - Ralph Marlett:
EBT: A comprehensive test generation technique for highly sequential circuits. 335-339 - Miroslaw Malek, Ajoy K. Bose:
Functional simulation and fault diagnosis. 340-346 - Akihiko Yamada, Nobuo Wakatsuki, T. Fukui, Shigehiro Funatsu:
Automatic System Level Test Generation and Fault Location for Large Digital Systems. 347-352 - H. Eisenberg:
CADMON: Improving the CAD system human interface. 353-358 - Ronald R. Willis:
DAS: An automated system to support design analysis. 359-365 - Anthony A. Lekkos, Carl M. Peters:
How to develop module logic using pseudo-code and stepwise refinement. 366-370 - Henry Kleine:
Automating the software design process by means of software design and documentation language. 371-379 - Joe Clema, Stephen Zissos:
ASCE Avionic System Configuration Evaluation. 380-385 - Robert C. Chen, James E. Coffman:
Multi-sim, a dynamic multi-level simulator. 386-391 - Glenn R. Case, Jerry D. Stauffer:
SALOGS-IV-A program to perform logic simulation and fault diagnosis. 392-397 - David J. Evans:
Accurate simulation of flip-flop timing characteristics. 398-404 - Ants Koppel, Siddharth Shah, Prem Puri:
A high performance delay calculation software system for MOSFET digital logic chips. 405-417 - Mario Tokoro, Masayuki Sato, Masayuki Ishigami, Euji Tamura, Terunobu Ishimitsu, Hisashi Ohara:
A module level simulation technique for systems composed of LSI's and MSI's. 418-427 - Giuseppe Alia, P. Ciompi, Enrico Martinelli, F. Bernardini:
LSI components modelling in a three-valued functional simulation. 428-438 - A. Miara, Norbert Giambiasi:
Dynamic and deductive fault simulation. 439-443 - Jerry T. Harvel:
Classification of PCB types for cost effective solutions. 444-445 - Philippe Villers:
A minicomputer based Interactive Graphics System as used for electronic design and automation. 446-453 - David Raeger:
The design of a dense PCB using an interactive DA system. 454 - Lawrence Bernstein, Christine M. Yuhas:
Software Manufacturing. 455-462 - Dan C. Nash:
Topics in design automation data bases. 463-474 - Glenn David Bergland:
Structured design methodologies. 475-493
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-11-06 20:16 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
