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2020 – today
- 2020
[j105]Hideo Fujiwara, Katsuya Fujiwara, Toshinori Hosokawa:
Universal Testing for Linear Feed-Forward/Feedback Shift Registers. IEICE Trans. Inf. Syst. 103-D(5): 1023-1030 (2020)
2010 – 2019
- 2019
- [c157]Yuya Kinoshita, Toshinori Hosokawa, Hideo Fujiwara:
A Test Generation Method Based on k-Cycle Testing for Finite State Machines. IOLTS 2019: 232-235 - 2018
- [j104]Dong Xiang, Krishnendu Chakrabarty
, Hideo Fujiwara:
Fault-Tolerant Unicast-Based Multicast for Reliable Network-on-Chip Testing. ACM Trans. Design Autom. Electr. Syst. 23(6): 73:1-73:23 (2018) - 2017
- [j103]Hideo Fujiwara, Katsuya Fujiwara:
Synthesis and Enumeration of Generalized Shift Registers for Strongly Secure SR-Equivalents. IEICE Trans. Inf. Syst. 100-D(9): 2232-2236 (2017) - 2016
- [j102]Hideo Fujiwara, Katsuya Fujiwara:
Properties of Generalized Feedback Shift Registers for Secure Scan Design. IEICE Trans. Inf. Syst. 99-D(4): 1255-1258 (2016) - [j101]Hideo Fujiwara, Katsuya Fujiwara:
Realization of SR-Equivalents Using Generalized Shift Registers for Secure Scan Design. IEICE Trans. Inf. Syst. 99-D(8): 2182-2185 (2016) - [j100]Dong Xiang, Krishnendu Chakrabarty, Hideo Fujiwara:
Multicast-Based Testing and Thermal-Aware Test Scheduling for 3D ICs with a Stacked Network-on-Chip. IEEE Trans. Computers 65(9): 2767-2779 (2016) - [c156]Jun Nishimaki, Toshinori Hosokawa, Hideo Fujiwara:
A scheduling method for hierarchical testability based on test environment generation results. ETS 2016: 1-2 - [c155]Dong Xiang, Krishnendu Chakrabarty, Hideo Fujiwara:
A unified test and fault-tolerant multicast solution for network-on-chip designs. ITC 2016: 1-9 - 2015
- [j99]Debesh Kumar Das, Hideo Fujiwara:
One More Class of Sequential Circuits having Combinational Test Generation Complexity. J. Electron. Test. 31(3): 321-327 (2015) - [j98]Hideo Fujiwara, Katsuya Fujiwara:
Strongly Secure Scan Design Using Generalized Feed Forward Shift Registers. IEICE Trans. Inf. Syst. 98-D(10): 1852-1855 (2015) - [c154]Tetsuya Masuda, Jun Nishimaki, Toshinori Hosokawa, Hideo Fujiwara:
A Test Generation Method for Data Paths Using Easily Testable Functional Time Expansion Models and Controller Augmentation. ATS 2015: 37-42 - 2013
- [j97]Katsuya Fujiwara, Hideo Fujiwara:
Generalized Feed Forward Shift Registers and Their Application to Secure Scan Design. IEICE Trans. Inf. Syst. 96-D(5): 1125-1133 (2013) - [j96]Katsuya Fujiwara, Hideo Fujiwara, Hideo Tamamoto:
Secure and Testable Scan Design Utilizing Shift Register Quasi-equivalents. IPSJ Trans. Syst. LSI Des. Methodol. 6: 27-33 (2013) - [c153]Dong Xiang, Gang Liu, Krishnendu Chakrabarty, Hideo Fujiwara:
Thermal-aware test scheduling for NOC-based 3D integrated circuits. VLSI-SoC 2013: 96-101 - 2012
- [j95]Taavi Viilukas, Anton Karputkin, Jaan Raik, Maksim Jenihhin, Raimund Ubar, Hideo Fujiwara:
Identifying Untestable Faults in Sequential Circuits Using Test Path Constraints. J. Electron. Test. 28(4): 511-521 (2012) - [j94]Michiko Inoue, Akira Taketani, Tomokazu Yoneda, Hideo Fujiwara:
Test Pattern Ordering and Selection for High Quality Test Set under Constraints. IEICE Trans. Inf. Syst. 95-D(12): 3001-3009 (2012) - [j93]Hyunbean Yi, Tomokazu Yoneda, Michiko Inoue, Yasuo Sato, Seiji Kajihara, Hideo Fujiwara:
A Failure Prediction Strategy for Transistor Aging. IEEE Trans. Very Large Scale Integr. Syst. 20(11): 1951-1959 (2012) - 2011
- [j92]Michiko Inoue, Tomokazu Yoneda, Muneo Hasegawa, Hideo Fujiwara:
Balanced Secure Scan: Partial Scan Approach for Secret Information Protection. J. Electron. Test. 27(2): 99-108 (2011) - [j91]Chia Yee Ooi, Hideo Fujiwara:
A New Design-for-Testability Method Based on Thru-Testability. J. Electron. Test. 27(5): 583-598 (2011) - [j90]Marie Engelene J. Obien, Satoshi Ohtake, Hideo Fujiwara:
F-Scan: A DFT Method for Functional Scan at RTL. IEICE Trans. Inf. Syst. 94-D(1): 104-113 (2011) - [j89]Katsuya Fujiwara, Hideo Fujiwara, Hideo Tamamoto:
Differential Behavior Equivalent Classes of Shift Register Equivalents for Secure and Testable Scan Design. IEICE Trans. Inf. Syst. 94-D(7): 1430-1439 (2011) - [c152]Hideo Fujiwara, Katsuya Fujiwara, Hideo Tamamoto:
Secure scan design using shift register equivalents against differential behavior attack. ASP-DAC 2011: 818-823 - [c151]Jaan Raik, Anna Rannaste, Maksim Jenihhin, Taavi Viilukas, Raimund Ubar, Hideo Fujiwara:
Constraint-Based Hierarchical Untestability Identification for Synchronous Sequential Circuits. ETS 2011: 147-152 - [c150]Marie Engelene J. Obien, Satoshi Ohtake, Hideo Fujiwara:
F-Scan Test Generation Model for Delay Fault Testing at RTL Using Standard Full Scan ATPG. ETS 2011: 203 - [c149]Tomokazu Yoneda, Makoto Nakao, Michiko Inoue, Yasuo Sato, Hideo Fujiwara:
Temperature-Variation-Aware Test Pattern Optimization. ETS 2011: 214 - [c148]Tomokazu Yoneda, Keigo Hori, Michiko Inoue, Hideo Fujiwara:
Faster-than-at-speed test for increased test quality and in-field reliability. ITC 2011: 1-9 - 2010
- [j88]Hongxia Fang, Krishnendu Chakrabarty, Hideo Fujiwara:
RTL DFT Techniques to Enhance Defect Coverage for Functional Test Sequences. J. Electron. Test. 26(2): 151-164 (2010) - [j87]Ryoichi Inoue, Toshinori Hosokawa, Hideo Fujiwara:
A Fault Dependent Test Generation Method for State-Observable FSMs to Increase Defect Coverage under the Test Length Constraint. IEICE Trans. Inf. Syst. 93-D(1): 24-32 (2010) - [j86]Tomokazu Yoneda, Akiko Shuto, Hideyuki Ichihara, Tomoo Inoue, Hideo Fujiwara:
Design and Optimization of Transparency-Based TAM for SoC Test. IEICE Trans. Inf. Syst. 93-D(6): 1549-1559 (2010) - [j85]Hiroshi Iwata, Satoshi Ohtake, Hideo Fujiwara:
A Method of Path Mapping from RTL to Gate Level and Its Application to False Path Identification. IEICE Trans. Inf. Syst. 93-D(7): 1857-1865 (2010) - [c147]Fawnizu Azmadi Hussin, Thomas Edison Yu, Tomokazu Yoneda, Hideo Fujiwara:
RedSOCs-3D: Thermal-safe test scheduling for 3D-stacked SOC. APCCAS 2010: 264-267 - [c146]Hideo Fujiwara, Marie Engelene J. Obien:
Secure and testable scan design using extended de Bruijn graphs. ASP-DAC 2010: 413-418 - [c145]Hiroshi Iwata, Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara:
Bipartite Full Scan Design: A DFT Method for Asynchronous Circuits. Asian Test Symposium 2010: 206-211 - [c144]Tomokazu Yoneda, Michiko Inoue, Akira Taketani, Hideo Fujiwara:
Seed Ordering and Selection for High Quality Delay Test. Asian Test Symposium 2010: 313-318 - [c143]Zhiqiang You, Jiedi Huang, Michiko Inoue, Jishun Kuang, Hideo Fujiwara:
Capture in Turn Scan for Reduction of Test Data Volume, Test Application Time and Test Power. Asian Test Symposium 2010: 371-374 - [c142]Katsuya Fujiwara, Hideo Fujiwara, Marie Engelene J. Obien, Hideo Tamamoto:
SREEP: Shift Register Equivalents Enumeration and Synthesis Program for secure scan design. DDECS 2010: 193-196 - [c141]Satoshi Ohtake, Hiroshi Iwata, Hideo Fujiwara:
A synthesis method to propagate false path information from RTL to gate level. DDECS 2010: 197-200 - [c140]Hiroshi Iwata, Satoshi Ohtake, Hideo Fujiwara:
Enabling False Path Identification from RTL for Reducing Design and Test Futileness. DELTA 2010: 20-25 - [c139]Jaynarayan T. Tudu, Erik Larsson, Virendra Singh, Hideo Fujiwara:
Scan cell reordering to minimize peak power during test cycle: A graph theoretic approach. ETS 2010: 259 - [c138]Michiko Inoue, Akira Taketani, Tomokazu Yoneda, Hiroshi Iwata, Hideo Fujiwara:
Test pattern selection to optimize delay test quality with a limited size of test set. ETS 2010: 260 - [c137]Jaynarayan T. Tudu, Erik Larsson, Virendra Singh, Hideo Fujiwara:
Graph theoretic approach for scan cell reordering to minimize peak shift power. ACM Great Lakes Symposium on VLSI 2010: 73-78 - [c136]Hyunbean Yi, Tomokazu Yoneda, Michiko Inoue, Yasuo Sato, Seiji Kajihara, Hideo Fujiwara:
Aging test strategy and adaptive test scheduling for SoC failure prediction. IOLTS 2010: 21-26 - [c135]Marie Engelene J. Obien, Satoshi Ohtake, Hideo Fujiwara:
Constrained ATPG for functional RTL circuits using F-Scan. ITC 2010: 615-624 - [c134]Alodeep Sanyal, Krishnendu Chakrabarty, Mahmut Yilmaz, Hideo Fujiwara:
RT-level design-for-testability and expansion of functional test sequences for enhanced defect coverage. ITC 2010: 625-634 - [c133]Raghavendra Adiga, Gandhi Arpit, Virendra Singh, Kewal K. Saluja, Hideo Fujiwara, Adit D. Singh:
On Minimization of Test Application Time for RAS. VLSI Design 2010: 393-398 - [c132]Tomokazu Yoneda, Michiko Inoue, Yasuo Sato, Hideo Fujiwara:
Thermal-uniformity-aware X-filling to reduce temperature-induced delay variation for accurate at-speed testing. VTS 2010: 188-193
2000 – 2009
- 2009
- [c131]Yuki Yoshikawa, Satoshi Ohtake, Tomoo Inoue, Hideo Fujiwara:
Fast false path identification based on functional unsensitizability using RTL information. ASP-DAC 2009: 660-665 - [c130]Thomas Edison Yu, Tomokazu Yoneda, Krishnendu Chakrabarty, Hideo Fujiwara:
Test infrastructure design for core-based system-on-chip under cycle-accurate thermal constraints. ASP-DAC 2009: 793-798 - [c129]Michiko Inoue, Tomokazu Yoneda, Muneo Hasegawa, Hideo Fujiwara:
Partial Scan Approach for Secret Information Protection. ETS 2009: 143-148 - [c128]Hongxia Fang, Krishnendu Chakrabarty, Hideo Fujiwara:
RTL DFT techniques to enhance defect coverage for functional test sequences. HLDVT 2009: 160-165 - [c127]Yuki Yoshikawa, Satoshi Ohtake, Tomoo Inoue, Hideo Fujiwara:
A Synthesis Method to Alleviate Over-Testing of Delay Faults Based on RTL Don't Care Path Identification. VTS 2009: 71-76 - [c126]Michiko Inoue, Tsuyoshi Suzuki, Hideo Fujiwara:
Brief Announcement: Acceleration by Contention for Shared Memory Mutual Exclusion Algorithms. DISC 2009: 172-173 - 2008
- [j84]Fawnizu Azmadi Hussin, Tomokazu Yoneda, Alex Orailoglu, Hideo Fujiwara:
Scheduling Power-Constrained Tests through the SoC Functional Bus. IEICE Trans. Inf. Syst. 91-D(3): 736-746 (2008) - [j83]Tomokazu Yoneda, Kimihiko Masuda, Hideo Fujiwara:
Test Scheduling for Multi-Clock Domain SoCs under Power Constraint. IEICE Trans. Inf. Syst. 91-D(3): 747-755 (2008) - [j82]Masato Nakasato, Michiko Inoue, Satoshi Ohtake, Hideo Fujiwara:
Design for Testability Method to Avoid Error Masking of Software-Based Self-Test for Processors. IEICE Trans. Inf. Syst. 91-D(3): 763-770 (2008) - [j81]Thomas Edison Yu, Tomokazu Yoneda, Danella Zhao, Hideo Fujiwara:
Effective Domain Partitioning for Multi-Clock Domain IP Core Wrapper Design under Power Constraints. IEICE Trans. Inf. Syst. 91-D(3): 807-814 (2008) - [j80]Fawnizu Azmadi Hussin, Tomokazu Yoneda, Hideo Fujiwara:
On NoC Bandwidth Sharing for the Optimization of Area Cost and Test Application Time. IEICE Trans. Inf. Syst. 91-D(7): 1999-2007 (2008) - [j79]Fawnizu Azmadi Hussin, Tomokazu Yoneda, Hideo Fujiwara:
NoC-Compatible Wrapper Design and Optimization under Channel-Bandwidth and Test-Time Constraints. IEICE Trans. Inf. Syst. 91-D(7): 2008-2017 (2008) - [j78]Thomas Edison Yu, Tomokazu Yoneda, Krishnendu Chakrabarty, Hideo Fujiwara:
Thermal-Aware Test Access Mechanism and Wrapper Design Optimization for System-on-Chips. IEICE Trans. Inf. Syst. 91-D(10): 2440-2448 (2008) - [j77]Dong Xiang, Yang Zhao, Krishnendu Chakrabarty, Hideo Fujiwara:
A Reconfigurable Scan Architecture With Weighted Scan-Enable Signals for Deterministic BIST. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(6): 999-1012 (2008) - [j76]Hideo Fujiwara, Hiroyuki Iwata, Tomokazu Yoneda, Chia Yee Ooi:
A Nonscan Design-for-Testability Method for Register-Transfer-Level Circuits to Guarantee Linear-Depth Time Expansion Models. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(9): 1535-1544 (2008) - [c125]Yu Hu, Xiang Fu, Xiaoxin Fan, Hideo Fujiwara:
Localized random access scan: Towards low area and routing overhead. ASP-DAC 2008: 565-570 - [c124]Jaan Raik, Hideo Fujiwara, Raimund Ubar, Anna Krivenko:
Untestable Fault Identification in Sequential Circuits Using Model-Checking. ATS 2008: 21-26 - [c123]Ryoichi Inoue, Toshinori Hosokawa, Hideo Fujiwara:
A Test Generation Method for State-Observable FSMs to Increase Defect Coverage under the Test Length Constraint. ATS 2008: 27-34 - [c122]Thomas Edison Yu, Tomokazu Yoneda, Satoshi Ohtake, Hideo Fujiwara:
Identifying Non-Robust Untestable RTL Paths in Circuits with Multi-cycle Paths. ATS 2008: 125-130 - [c121]Tomokazu Yoneda, Hideo Fujiwara:
Wrapper and TAM Co-Optimization for Reuse of SoC Functional Interconnects. DATE 2008: 1366-1369 - 2007
- [j75]Ilia Polian, Hideo Fujiwara:
Functional Constraints vs. Test Compression in Scan-Based Delay Testing. J. Electron. Test. 23(5): 445-455 (2007) - [j74]Masato Nakasato, Satoshi Ohtake, Kewal K. Saluja, Hideo Fujiwara:
Acceleration of Test Generation for Sequential Circuits Using Knowledge Obtained from Synthesis for Testability. IEICE Trans. Inf. Syst. 90-D(1): 296-305 (2007) - [j73]Chia Yee Ooi, Thomas Clouqueur, Hideo Fujiwara:
Analysis of Test Generation Complexity for Stuck-At and Path Delay Faults Based on tauk-Notation. IEICE Trans. Inf. Syst. 90-D(8): 1202-1212 (2007) - [j72]Dong Xiang, Kaiwei Li, Jiaguang Sun, Hideo Fujiwara:
Reconfigured Scan Forest for Test Application Cost, Test Data Volume, and Test Power Reduction. IEEE Trans. Computers 56(4): 557-562 (2007) - [j71]Dong Xiang, Mingjing Chen, Hideo Fujiwara:
Using Weighted Scan Enable Signals to Improve Test Effectiveness of Scan-Based BIST. IEEE Trans. Computers 56(12): 1619-1628 (2007) - [j70]Dong Xiang, Kaiwei Li, Hideo Fujiwara, Krishnaiyan Thulasiraman, Jiaguang Sun:
Constraining Transition Propagation for Low-Power Scan Testing Using a Two-Stage Scan Architecture. IEEE Trans. Circuits Syst. II Express Briefs 54-II(5): 450-454 (2007) - [j69]Yoshiyuki Nakamura, Thomas Clouqueur, Kewal K. Saluja, Hideo Fujiwara:
Diagnosing At-Speed Scan BIST Circuits Using a Low Speed and Low Memory Tester. IEEE Trans. Very Large Scale Integr. Syst. 15(7): 790-800 (2007) - [c120]Dan Zhao, Unni Chandran, Hideo Fujiwara:
Shelf Packing to the Design and Optimization of A Power-Aware Multi-Frequency Wrapper Architecture for Modular IP Cores. ASP-DAC 2007: 714-719 - [c119]Fawnizu Azmadi Hussin, Tomokazu Yoneda, Alex Orailoglu, Hideo Fujiwara:
Core-Based Testing of Multiprocessor System-on-Chips Utilizing Hierarchical Functional Buses. ASP-DAC 2007: 720-725 - [c118]Yuki Yoshikawa, Satoshi Ohtake, Hideo Fujiwara:
False Path Identification using RTL Information and Its Application to Over-testing Reduction for Delay Faults. ATS 2007: 65-68 - [c117]Dan Zhao, Ronghua Huang, Hideo Fujiwara:
Multi-Frequency Modular Testing of SoCs by Dynamically Reconfiguring Multi-Port ATE. ATS 2007: 107-110 - [c116]Thomas Edison Yu, Tomokazu Yoneda, Krishnendu Chakrabarty, Hideo Fujiwara:
Thermal-Safe Test Access Mechanism and Wrapper Co-optimization for System-on-Chip. ATS 2007: 187-192 - [c115]Tomokazu Yoneda, Yuusuke Fukuda, Hideo Fujiwara:
Test Scheduling for Memory Cores with Built-In Self-Repair. ATS 2007: 199-206 - [c114]Toshinori Hosokawa, Ryoichi Inoue, Hideo Fujiwara:
Fault-dependent/independent Test Generation Methods for State Observable FSMs. ATS 2007: 275-280 - [c113]Dong Xiang, Krishnendu Chakrabarty, Dianwei Hu, Hideo Fujiwara:
Scan Testing for Complete Coverage of Path Delay Faults with Reduced Test Data Volume, Test Application Time, and Hardware Cost. ATS 2007: 329-334 - [c112]Fawnizu Azmadi Hussin, Tomokazu Yoneda, Hideo Fujiwara:
Area Overhead and Test Time Co-Optimization through NoC Bandwidth Sharing. ATS 2007: 459-462 - [c111]Hiroyuki Iwata, Tomokazu Yoneda, Hideo Fujiwara:
A DFT Method for Time Expansion Model at Register Transfer Level. DAC 2007: 682-687 - [c110]Tomokazu Yoneda, Masahiro Imanishi, Hideo Fujiwara:
Interactive presentation: An SoC test scheduling algorithm using reconfigurable union wrappers. DATE 2007: 231-236 - [c109]Fawnizu Azmadi Hussin, Tomokazu Yoneda, Hideo Fujiwara:
Optimization of NoC Wrapper Design under Bandwidth and Test Time Constraints. ETS 2007: 35-42 - [c108]Tsuyoshi Iwagaki, Satoshi Ohtake, Mineo Kaneko, Hideo Fujiwara:
Efficient path delay test generation based on stuck-at test generation using checker circuitry. ICCAD 2007: 418-423 - [c107]Dan Zhao, Ronghua Huang, Tomokazu Yoneda, Hideo Fujiwara:
Power-Aware Multi-Frequency Heterogeneous SoC Test Framework Design with Floor-Ceiling Packing. ISCAS 2007: 2942-2945 - [c106]Dong Xiang, Yang Zhao, Kaiwei Li, Hideo Fujiwara:
Fast and effective fault simulation for path delay faults based on selected testable paths. ITC 2007: 1-10 - [c105]Thomas Edison Yu, Tomokazu Yoneda, Danella Zhao, Hideo Fujiwara:
Using Domain Partitioning in Wrapper Design for IP Cores Under Power Constraints. VTS 2007: 369-374 - [c104]Tomokazu Yoneda, Akiko Shuto, Hideyuki Ichihara, Tomoo Inoue, Hideo Fujiwara:
TAM Design and Optimization for Transparency-Based SoC Test. VTS 2007: 381-388 - 2006
- [j68]Yoshiyuki Nakamura, Thomas Clouqueur, Kewal K. Saluja, Hideo Fujiwara:
Error Identification in At-Speed Scan BIST Environment in the Presence of Circuit and Tester Speed Mismatch. IEICE Trans. Inf. Syst. 89-D(3): 1165-1172 (2006) - [j67]Masahide Miyazaki, Tomokazu Yoneda, Hideo Fujiwara:
A Memory Grouping Method for Reducing Memory BIST Logic of System-on-Chips. IEICE Trans. Inf. Syst. 89-D(4): 1490-1497 (2006) - [j66]Zhiqiang You, Tsuyoshi Iwagaki, Michiko Inoue, Hideo Fujiwara:
A Low Power Deterministic Test Using Scan Chain Disable Technique. IEICE Trans. Inf. Syst. 89-D(6): 1931-1939 (2006) - [j65]Yoshiyuki Nakamura, Jacob Savir, Hideo Fujiwara:
Effect of BIST Pretest on IC Defect Level. IEICE Trans. Inf. Syst. 89-D(10): 2626-2636 (2006) - [j64]Tomokazu Yoneda, Hideo Fujiwara:
Design for consecutive transparency method of RTL circuits. Syst. Comput. Jpn. 37(2): 1-10 (2006) - [j63]Erik Larsson, Hideo Fujiwara:
System-on-chip test scheduling with reconfigurable core wrappers. IEEE Trans. Very Large Scale Integr. Syst. 14(3): 305-309 (2006) - [j62]Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara:
Instruction-Based Self-Testing of Delay Faults in Pipelined Processors. IEEE Trans. Very Large Scale Integr. Syst. 14(11): 1203-1215 (2006) - [c103]Masahide Miyazaki, Tomokazu Yoneda, Hideo Fujiwara:
A memory grouping method for sharing memory BIST logic. ASP-DAC 2006: 671-676 - [c102]Chia Yee Ooi, Hideo Fujiwara:
A New Scan Design Technique Based on Pre-Synthesis Thru Functions. ATS 2006: 163-168 - [c101]Hideo Fujiwara, Jiaguang Sun, Krishnendu Chakrabarty, Yang Zhao, Dong Xiang:
Compressing Test Data for Deterministic BIST Using a Reconfigurable Scan Arhcitecture. ATS 2006: 299-306 - [c100]Masato Nakazato, Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara:
Design for Testability of Software-Based Self-Test for Processors. ATS 2006: 375-380 - [c99]Yoshiyuki Nakamura, Thomas Clouqueur, Kewal K. Saluja, Hideo Fujiwara:
Diagnosing At-Speed Scan BIST Circuits Using a Low Speed and Low Memory Tester. ATS 2006: 409-414 - [c98]Tomokazu Yoneda, Kimihiko Masuda, Hideo Fujiwara:
Power-constrained test scheduling for multi-clock domain SoCs. DATE 2006: 297-302 - [c97]Ilia Polian, Hideo Fujiwara:
Functional constraints vs. test compression in scan-based delay testing. DATE 2006: 1039-1044 - [c96]Mariane Comte, Satoshi Ohtake, Hideo Fujiwara, Michel Renovell:
Electrical Behavior of GOS Fault affected Domino Logic Cell. DELTA 2006: 183-189 - [c95]Ilia Polian, Bernd Becker, Masato Nakasato, Satoshi Ohtake, Hideo Fujiwara:
Low-Cost Hardening of Image Processing Applications Against Soft Errors. DFT 2006: 274-279 - [c94]Fawnizu Azmadi Hussin, Tomokazu Yoneda, Alex Orailoglu, Hideo Fujiwara:
Power-Constrained SOC Test Schedules through Utilization of Functional Buses. ICCD 2006: 230-236 - [c93]Chia Yee Ooi, Hideo Fujiwara:
A New Class of Sequential Circuits with Acyclic Test Generation Complexity. ICCD 2006: 425-431 - [c92]Dong Xiang, Kaiwei Li, Hideo Fujiwara, Jiaguang Sun:
Generating Compact Robust and Non-Robust Tests for Complete Coverage of Path Delay Faults Based on Stuck-at Tests. ICCD 2006: 446-451 - [c91]Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara:
Broadside Transition Test Generation for Partial Scan Circuits through Stuck-at Test Generation. VLSI-SoC (Selected Papers) 2006: 301-316 - [c90]Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara:
A New Test Generation Model for Broadside Transition Testing of Partial Scan Circuits. VLSI-SoC 2006: 308-313 - [c89]Yoshiyuki Nakamura, Jacob Savir, Hideo Fujiwara:
BIST Pretest of ICs: Risks and Benefits. VTS 2006: 142-149 - 2005
- [j61]Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara:
Delay Fault Testing of Processor Cores in Functional Mode. IEICE Trans. Inf. Syst. 88-D(3): 610-618 (2005) - [j60]