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ORCIDDFT 1995: Lafayette, LA, USA
- 1995 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 1995, Lafayette, LA, USA, November 13-15, 1995. IEEE Computer Society 1995, ISBN 0-8186-7107-6
Session 1: Critical Area Analysis
- Frederic Duvivier, M. Rivier:
Approximation of critical area of ICs with simple parameters extracted from the layout. 1-9 - Igor Bubel, Wojciech Maly, Thomas Waas, Pranab K. Nag, Hans Hartmann, Doris Schmitt-Landsiedel, Susanne Griep:
AFFCCA: a tool for critical area analysis with circular defects and lithography deformed layout. 10-18 - Pranab K. Nag, Wojciech Maly:
Hierarchical extraction of critical area for shorts in very large ICs. 19-27 - Gerard A. Allan, Anthony J. Walton:
Hierarchical critical area extraction with the EYE tool. 28-36
Session 2: Defect Sensitivity and Reliability
- Glenn H. Chapman, D. E. Bergen, K. Fang:
Wafer-scale integration defect avoidance tradeoffs between laser links and Omega network switching. 37-45 - Israel A. Wagner, Israel Koren:
The effect of spot defects on the parametric yield of long interconnection lines. 46-54 - Gerard A. Allan, Anthony J. Walton:
Critical area extraction of extra material soft faults. 55-62 - Aurobindo Dasgupta, Ramesh Karri
:
Switch level hot-carrier reliability enhancement of VLSI circuits. 63-71
Session 3: Fault Tolerant Architectures
- Anna Antola, Luca Breveglieri:
A model for the evaluation of fault tolerance in the FERMI system. 72-80 - Ragini Narasimhan, Daniel J. Rosenkrantz, S. S. Ravi:
Efficient algorithms for analyzing and synthesizing fault-tolerant datapaths. 81-89 - Luigi Dadda, Vincenzo Piuri:
Bit-modular defect/fault-tolerant convolvers. 90-98
Session 4: Fault Tolerant Arrays
- Mariagiovanna Sami, Fausto Distante, Renato Stefanelli:
A Channel-Constrained Reconfiguration Approach for Processing Arrays. 99-107 - Itsuo Takanami, Tadayoshi Horita:
Reconfigurable architectures for mesh-arrays with PE and link faults. 108-116 - Nobuo Tsuda, Tsutomu Ishikawa, Yukihiro Nakamura:
Totally defect-tolerant arrays capable of quick broadcasting. 117-125 - Adit D. Singh:
ADTS: an array defect-tolerance scheme for wafer scale gate arrays. 126-136 - Jai-Hoon Kim, Fabrizio Lombardi, Nitin H. Vaidya:
An improved approach to fault tolerant rank order filtering on a SIMD mesh processor. 137-145
Session 5: Yield Projection and Enhancement
- Neil Harrison:
Yield projection from defect monitors: the influence of gross defects [BiCMOS process]. 146-154 - Dinesh D. Gaitonde, D. M. H. Walker, Wojciech Maly:
Accurate yield estimation of circuits with redundancy. 155-163 - M. Baxter, D. Muir:
Using defect density modelling to drive the optimisation of circuit layout, maximising yield. 164-172 - Zhan Chen, Israel Koren:
Layer assignment for yield enhancement. 173-180
Session 6: Fault Tolerant Techniques
- David Wessels, Jon C. Muzio:
Analyzing and improving delay defect tolerance in pipelined combinational circuits. 181-188 - Yves Blaquière, Gabriel Gagné, Yvon Savaria, Claude Évéquoz:
Cost analysis of a new algorithmic-based soft-error tolerant architecture. 189-197 - Yuang-Ming Hsu, Vincenzo Piuri, Earl E. Swartzlander Jr.:
Efficient time redundancy for error correcting inner-product units and convolvers. 198-206 - Manoj Franklin:
A study of time redundant fault tolerance techniques for superscalar processors. 207-215 - Hannu H. Kari, Heikki Saikkonen, Sungsoo Kim, Fabrizio Lombardi:
Repair algorithms for mirrored disk systems. 216-224
Session 7: Testing Techniques
- Xiao-Tao Chen, Wei-Kang Huang, Fabrizio Lombardi, Xiao Sun:
A row-based FPGA for single and multiple stuck-at fault detection. 225-233 - Stephanie R. Goldberg, Shambhu J. Upadhyaya:
Utilizing spares in multichip modules for the dual function of fault coverage and fault diagnosis. 234-242 - Claude Thibeault, A. Payeur:
FFT-based test of a yield monitor circuit. 243-251 - P. Brahic, Régis Leveugle, Gabriele Saucier:
Design of defect-tolerant scan chains for MCMs with an active substrate. 252-260 - Thomas A. Ziaja, Earl E. Swartzlander Jr.:
Characterization and analysis of errors in circuit test. 261-268
Session 8: Self Checking and Coding Techniques
- Cristiana Bolchini, R. Montandon, Fabio Salice, Donatella Sciuto:
Self-checking FSMs based on a constant distance state encoding. 269-277 - Guilang Feng, Sihai Xiao, Xiaofa Shi, T. R. N. Rao:
Constructions of the SbEC-DbED and DbEC codes, and their applications. 278-286 - Cecilia Metra, Michele Favalli, Bruno Riccò:
Novel Berger code checker. 287-295 - Jien-Chung Lo:
Single fault masking logic designs with error correcting codes. 296-
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