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Tadayoshi Horita
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2010 – 2019
- 2016
- [j9]Itsuo Takanami, Tadayoshi Horita, Masakazu Akiba, Mina Terauchi, Tsuneo Kanno:
A Built-in Self-repair Circuit for Restructuring Mesh-Connected Processor Arrays by Direct Spare Replacement. Trans. Comput. Sci. 27: 97-119 (2016) - 2015
- [j8]Tadayoshi Horita, Itsuo Takanami, Masakazu Akiba, Mina Terauchi, Tsuneo Kanno:
An FPGA-Based Multiple-Weight-and-Neuron-Fault Tolerant Digital Multilayer Perceptron (Full Version). Trans. Comput. Sci. 25: 148-171 (2015) - 2014
- [j7]Tadayoshi Horita, Itsuo Takanami, Kazuhiro Nishimura:
Multilayer Perceptrons Which Are Tolerant to Multiple Faults and Learnings to Realize Them. Trans. Comput. Sci. 22: 42-63 (2014) - [c15]Tadayoshi Horita, Itsuo Takanami, Masakazu Akiba, Mina Terauchi, Tsuneo Kanno:
A GPGPU-Based Acceleration of Fault-Tolerant MLP Learnings. MCSoC 2014: 245-252 - 2013
- [j6]Tadayoshi Horita, Itsuo Takanami:
An FPGA-based multiple-weight-and-neuron-fault tolerant digital multilayer perceptron. Neurocomputing 99: 570-574 (2013) - 2012
- [c14]Itsuo Takanami, Tadayoshi Horita:
A Built-in Circuit for Self-Repairing Mesh-Connected Processor Arrays by Direct Spare Replacement. PRDC 2012: 96-104 - 2011
- [j5]Tadayoshi Horita, Itsuo Takanami:
An FPGA-Based Fault-Tolerant 2D Systolic Array for Matrix Multiplications. Trans. Comput. Sci. 13: 108-124 (2011) - 2010
- [j4]Tadayoshi Horita, Itsuo Takanami:
An FPGA-based fast classifier with high generalization property. SIGARCH Comput. Archit. News 38(4): 21-26 (2010)
2000 – 2009
- 2009
- [c13]Tadayoshi Horita, Itsuo Takanami:
An Implementation of a Fault-Tolerant 2D Systolic Array on FPGAs and Its Evaluation. PDPTA 2009: 136-142 - [c12]Tadayoshi Horita, Koichi Kitano, Koji Teramoto:
A Computer Cluster for Tests of Parallel Programming Environments Including Operating Systems. PDPTA 2009: 422-426 - [c11]Kazuhiro Nishimura, Tadayoshi Horita, Masato Otsu, Itsuo Takanami:
Novel Value Injection Learning Methods Which Make Multilayer Neural Networks Multiple-Weight-and-Neuron-Fault Tolerant. PDPTA 2009: 546-552 - 2008
- [j3]Tadayoshi Horita, Yuuji Katou, Itsuo Takanami:
An Analysis for Fault-Tolerant 3D Processor Arrays Using 1.5-Track Switches. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(2): 623-632 (2008) - [j2]Tadayoshi Horita, Itsuo Takanami, Masatoshi Mori:
Learning Algorithms Which Make Multilayer Neural Networks Multiple-Weight-and-Neuron-Fault Tolerant. IEICE Trans. Inf. Syst. 91-D(4): 1168-1175 (2008) - 2006
- [c10]Tadayoshi Horita, Takurou Murata, Itsuo Takanami:
A Multiple-Weight-and-Neuron-Fault Tolerant Digital Multilayer Neural Network. DFT 2006: 554-562 - 2001
- [c9]Tadayoshi Horita, Itsuo Takanami:
Analytical Results for Reconfiguration of E-11/2- Track Switch Torus Arrays with Multiple Fault Types. PRDC 2001: 233-240 - 2000
- [j1]Tadayoshi Horita, Itsuo Takanami:
Fault-Tolerant Processor Arrays Based on the 1½-Track Switches with Flexible Spare Distributions. IEEE Trans. Computers 49(6): 542-552 (2000) - [c8]Tadayoshi Horita, Itsuo Takanami:
A System for Efficiently Self-Reconstructing E-1½-Track Switch Torus Arrays. ISPAN 2000: 44-49 - [c7]Tadayoshi Horita, Itsuo Takanami:
A System for Efficiently Self-Reconstructing 1½-Track Switch Torus Arrays. PDPTA 2000
1990 – 1999
- 1999
- [c6]Tadayoshi Horita, Itsuo Takanami:
Fault Tolerant Processor Arrays Based on 1 1/2-Track Switch with Generalized Spare Distributions. ISPAN 1999: 135-137 - 1997
- [c5]Itsuo Takanami, Tadayoshi Horita:
Self-reconstruction of mesh-arrays with 1 1/2 -track switches by digital neural circuits. DFT 1997: 218-226 - [c4]Tadayoshi Horita, Itsuo Takanami:
A Polynomial Time Algorithm for Reconfiguring the 1 1/2 Track-Switch Model with PE and Bus faults. ISPAN 1997: 16-22 - [c3]Itsuo Takanami, Tadayoshi Horita:
A built-in self-reconfigurable scheme for 3D mesh arrays. ISPAN 1997: 458-464 - 1996
- [c2]Tadayoshi Horita, Itsuo Takanami:
Reconfiguration of 1 1/2 track-switch mesh-arrays with PE and bus faults. DFT 1996: 335- - 1995
- [c1]Itsuo Takanami, Tadayoshi Horita:
Reconfigurable architectures for mesh-arrays with PE and link faults. DFT 1995: 108-116
Coauthor Index
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