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ORCIDDSD 2002: Dortmund, Germany
- 2002 Euromicro Symposium on Digital Systems Design (DSD 2002), Systems-on-Chip, 4-6 September 2002, Dortmund, Germany. IEEE Computer Society 2002, ISBN 0-7695-1790-0
Plenary - Keynote Session I
- Ulf Schlichtmann
:
Systems Are Made from Transistors: UDSM Technology Creates New Challenges for Library and IC Development. 2-3
Processor and Memory Architectures
- Daranee Hormdee, Jim D. Garside, Stephen B. Furber:
An Asynchronous Victim Cache. 4-11 - Ali Habibi, Sofiène Tahar, Adel Ghazel:
Formal Verification of a DSP Chip Using an Iterative Approach. 12-19 - Kenneth B. Kent, Micaela Serra:
Hardware Architecture for Java in a Hardware/Software Co-Design of the Virtual Machine. 20-27 - Jarno Vanne, Eero Aho, Kimmo Kuusilinna, Timo D. Hämäläinen:
Enhanced Configurable Parallel Memory Architecture. 28-37
Partitioning and Decomposition
- Rolf Drechsler, Wolfgang Günther, Thomas Eschbach, Lothar Linhard, Gerhard Angst:
Recursive Bi-Partitioning of Netlists for Large Number of Partitions. 38-44 - Ivan Z. Milentijevic, Vladimir M. Ciric, Teufik Tokic, Oliver M. Vojinovic:
Folded Bit-Plane FIR Filter Architecture with Changeable Folding Factor. 45-52 - Yinshui Xia, A. E. A. Almaini:
Best Polarity for Low Power XOR Gate Decomposition. 53-59 - José Ignacio Hidalgo, Juan Lanchares, Aitor Ibarra, Román Hermida:
A Hybrid Evolutionary Algorithm for Multi-FPGA Systems Design. 60-69
Special Architectures
- Matías J. Garrido, César Sanz, Marcos Jiménez, Juan M. Meneses:
A Flexible Architecture for H.263 Video Coding. 70-77 - Omar Mansour, Egbert Molenkamp, Thijs Krol:
The Synthesis of a Hardware Scheduler for Non-Manifest Loops. 78-85 - Juha-Pekka Soininen, Antti Pelkonen, Jussi Roivainen:
Configurable Memory Organisation for Communication Applications. 86-93 - Maik Boden, Jörg Schneider, Klaus Feske, Steffen Rülke:
Enhanced Reusability for SoC-Based HW/SW Co-Design. 94-101
System Specification and Modelling
- Per Andersson, Krzysztof Kuchcinski, Klas Nordberg, Patrick Doherty:
Integrating a Computational Model and a Run Time System for Image Processing on a UAV. 102-109 - Loe M. G. Feijs, Paul Gorissen, Joachim Trescher:
Specification and Simulation of Microprocessor Operations and Parallel Instructions. 110-117 - Martyn Edwards, Benjamin Fozard:
Rapid Prototyping of Mixed Hardware and Software Systems. 118-125 - Ilia Oussorov, Wolfgang Raab, J. A. Ulrich Hachmann, Alex Kravtsov:
Integration of Instruction Set Simulators into SystemC High Level Models. 126-131
Parallel Processor Architectures
- Bart D. Theelen, A. C. Verschueren:
Architecture Design of a Scalable Single-Chip Multi-Processor. 132-139 - Ari Wahyudi, Amos Omondi:
Parallel Multimedia Processor Using Customised Infineon TriCores. 140-147 - Manuel Lois Anido, Alexander Paar, Nader Bagherzadeh:
Improving the Operation Autonomy of SIMD Processing Elements by Using Guarded Instructions and Pseudo Branches. 148-155 - Dmitry Cheresiz, Ben H. H. Juurlink, Stamatis Vassiliadis, Harry A. G. Wijshoff:
Implementation of a Streaming Execution Unit. 156-165
Verification and Test
- Josef Strnadel, Zdenek Kotásek:
Testability Improvements Based on the Combination of Analytical and Evolutionary Approaches at RT Level. 166-173 - Roman Goot, Ilya Levin, Sergei Ostanin:
Fault Latencies of Concurrent Checking FSMs. 174-179 - Paul Amblard, Fabienne Lagnier, Michel Lévy:
Using Formal Tools to Study Complex Circuits Behaviour. 180-186 - André Schneider, Karl-Heinz Diener, Eero Ivask, Raimund Ubar, Elena Gramatová, Thomas Hollstein, Wieslaw Kuzmicz, Zebo Peng:
Integrated Design and Test Generation Under Internet Based Environment MOSCITO. 187-195
Plenary - Keynote Session II
- Paul Wielage, Kees Goossens:
Networks on Silicon: Blessing or Nightmare? 196-200 - Peter Marwedel:
Embedded Software: How To Make It Efficient? 201-209
Filter and Arithmetic Circuits
- Shoji Goto, Takashi Yamada, Norihisa Takayarna, Yoshifumi Matsushita, Yasoo Harada, Hiroto Yasuura:
A Design for a Low-Power Digital Matched Filter Applicable to W-CDMA. 210-217 - Daniel Piso Fernandez, José-Alejandro Piñeiro, Javier D. Bruguera:
Analysis of the Impact of Different Methods for Division/Square Root Computation in the Performance of a Superscalar Microprocessor. 218-225 - Nadia Nedjah, Luiza de Macedo Mourelle:
Reconfigurable Hardware Implementation of Montgomery Modular Multiplication and Parallel Binary Exponentiation. 226-235
Circuit Synthesis and Optimisation
- Dragan Jankovic, Radomir S. Stankovic, Rolf Drechsler:
Decision Diagram Optimization Using Copy Properties. 236-243 - Jacqueline E. Rice, Jon C. Muzio:
Use of the Autocorrelation Function in the Classification of Switching Functions. 244-251 - Aitor Ibarra, José M. Mendías, Juan Lanchares, José Ignacio Hidalgo, Román Hermida:
Optimization of Equational Specifications Using Genetic Techniques. 252-258 - Pawel Kerntopf:
Synthesis of Multipurpose Reversible Logic Gates. 259-267
Reconfigurable Computing Architectures
- Domingo Benitez:
Performance of Remote FPGA-Based Coprocessors for Image-Processing Applications. 268-275 - Oswaldo Cadenas, Graham M. Megson:
Improving mW/MHz Ratio in FPGAs Pipelined Designs. 276-282 - M. A. Hannan Bin Azhar, Keith R. Dimond:
Design of an FPGA Based Adaptive Neural Controller for Intelligent Robot Navigation. 283-290 - Ernest Jamro, Kazimierz Wiatr:
Constant Coefficient Convolution Implemented in FPGAs. 291-298 - Peter Green, M. Vakondios, Martyn Edwards:
An Evaluation of an FPGA Run-Time Support System. 299-307
High Level Synthesis
- José M. Mendías, Román Hermida, María C. Molina, Olga Peñalba:
Efficient Verification of Scheduling, Allocation and Binding in High-Level Synthesis. 308-315 - Azeddien M. Sllame, Vladimír Drábek:
An Efficient List-Based Scheduling Algorithm for High-Level Synthesis. 316-323 - Olga Peñalba, José M. Mendías, Román Hermida:
Source Code Transformation to Improve Conditional Hardware Reuse. 324-331
Panel - Systems-on-Chip
Poster Session
- Zeljko Vujovic:
Work Out of the Algorithm Based on A-Mod for Detection Borderlines in Images Provided by the Intravascular Ultrasound System (IVUS) with 64 Transducers. 332-336 - Rolf Drechsler, Daniel Große:
Reachability Analysis for Formal Verification of SystemC. 337-340 - Toshinori Sato, Itsujiro Arita:
Simplifying Instruction Issue Logic in Superscalar Processors. 341-346 - Martin Feldhofer, Thomas Trathnigg, Bernd Schnitzer:
A Self-Timed Arithmetic Unit for Elliptic Curve Cryptography. 347-350 - Giuseppe Notarangelo, Marco Gibilaro, Francesco Pappalardo, Agatino Pennisi, Gaetano Palumbo:
Low Power Strategy for a TFT Controller. 351-354 - Khushwinder Jasrotia, Jianwen Zhu:
Hardware Implementation of a Memory Allocator. 355-358 - Mariusz Chyzy, Witold Kosinski:
Evolutionary Algorithm for State Assignment of Finite State Machines. 359-363
Specification and Modelling
- Ronny Frevert, Steffen Rülke, Torsten Schäfer, Frank Dresig:
Use of HDL Code Checkers to Support the IP Entrance Check - A Requirement Analysis. 364-370 - Mark Verhappen, P. H. A. van der Putten, Jeroen Voeten:
On the Fundamental Design Gap in Terabit per Second Packet Switching. 371-379
Synthesis and Algorithms
- Rajendra S. Katti:
Speeding up Elliptic Cryptosystems Using a New Signed Binary Representation for Integers. 380-384 - María C. Molina, José M. Mendías, Román Hermida:
Bit-Level Allocation of Multiple-Precision Specifications. 385-392
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