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Raimund Ubar
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2020 – today
- 2024
- [b1]Raimund Ubar, Jaan Raik, Maksim Jenihhin, Artur Jutman:
Structural Decision Diagrams in Digital Test - Theory and Applications. Springer 2024, ISBN 978-3-031-44733-4, pp. 1-572 - 2022
- [c148]Adeboye Stephen Oyeniran, Maksim Jenihhin, Jaan Raik, Raimund Ubar:
High-Level Fault Diagnosis in RISC Processors with Implementation-Independent Functional Test. ISVLSI 2022: 32-37 - 2021
- [c147]Maksim Jenihhin, Adeboye Stephen Oyeniran, Jaan Raik, Raimund Ubar:
Implementation-Independent Test Generation for a Large Class of Faults in RISC Processor Modules. DSD 2021: 557-561 - [i5]Ahmet Cagri Bagbaba, Maksim Jenihhin, Raimund Ubar, Christian Sauer:
Representing Gate-Level SET Faults by Multiple SEU Faults at RTL. CoRR abs/2103.05106 (2021) - 2020
- [j30]Adeboye Stephen Oyeniran
, Raimund Ubar, Maksim Jenihhin, Jaan Raik:
High-Level Implementation-Independent Functional Software-Based Self-Test for RISC Processors. J. Electron. Test. 36(1): 87-103 (2020) - [j29]Lembit Jürimägi, Raimund Ubar, Maksim Jenihhin, Jaan Raik:
Calculation of probabilistic testability measures for digital circuits with Structurally Synthesized BDDs. Microprocess. Microsystems 77: 103117 (2020) - [c146]Adeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin, Jaan Raik:
Implementation-Independent Functional Test for Transition Delay Faults in Microprocessors. DSD 2020: 646-650 - [c145]Ahmet Cagri Bagbaba
, Maksim Jenihhin, Raimund Ubar, Christian Sauer:
Representing Gate-Level SET Faults by Multiple SEU Faults at RTL. IOLTS 2020: 1-6 - [i4]Cemil Cem Gürsoy, Maksim Jenihhin, Adeboye Stephen Oyeniran, Davide Piumatti, Jaan Raik, Matteo Sonza Reorda, Raimund Ubar:
New categories of Safe Faults in a processor-based Embedded System. CoRR abs/2009.11621 (2020)
2010 – 2019
- 2019
- [c144]Cemil Cem Gürsoy
, Maksim Jenihhin, Adeboye Stephen Oyeniran, Davide Piumatti, Jaan Raik
, Matteo Sonza Reorda
, Raimund Ubar
:
New categories of Safe Faults in a processor-based Embedded System. DDECS 2019: 1-4 - [c143]Raimund Ubar
, Lembit Jürimägi
, Adeniyi Olanrewaju Adekoya, Maksim Jenihhin:
True Path Tracing in Structurally Synthesized BDDs for Testability Analysis of Digital Circuits. DSD 2019: 492-499 - [c142]Adeboye Stephen Oyeniran, Raimund Ubar
, Maksim Jenihhin, Cemil Cem Gürsoy
, Jaan Raik
:
High-Level Combined Deterministic and Pseudo-exhuastive Test Generation for RISC Processors. ETS 2019: 1-6 - [c141]Lembit Jürimägi
, Raimund Ubar
, Maksim Jenihhin, Jaan Raik
, Sergei Devadze, Adeboye Stephen Oyeniran:
Application Specific True Critical Paths Identification in Sequential Circuits. IOLTS 2019: 299-304 - [c140]Adeboye Stephen Oyeniran, Raimund Ubar
, Maksim Jenihhin, Cemil Cem Gürsoy
, Jaan Raik
:
Mixed-level identification of fault redundancy in microprocessors. LATS 2019: 1-6 - [c139]Lembit Jürimägi
, Raimund Ubar
, Vladimir Viies:
Equivalent Transformations of Structurally Synthesized BDDs and Applications. MECO 2019: 1-6 - [c138]Adeboye Stephen Oyeniran, Raimund Ubar
:
High-Level Functional Test Generation for Microprocessor Modules. MIXDES 2019: 356-361 - [c137]Adeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin, Jaan Raik:
On Test Generation for Microprocessors for Extended Class of Functional Faults. VLSI-SoC (Selected Papers) 2019: 21-44 - [c136]Adeboye Stephen Oyeniran, Raimund Ubar
, Maksim Jenihhin, Jaan Raik
:
Implementation-Independent Functional Test Generation for MSC Microprocessors. VLSI-SoC 2019: 82-87 - [i3]Adeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin, Cemil Cem Gürsoy, Jaan Raik:
Mixed-level identification of fault redundancy in microprocessors. CoRR abs/1907.12325 (2019) - [i2]Adeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin, Cemil Cem Gürsoy, Jaan Raik:
High-Level Combined Deterministic and Pseudoexhuastive Test Generation for RISC Processors. CoRR abs/1908.02986 (2019) - 2018
- [j28]Raimund Ubar
, Sergei Kostin, Maksim Jenihhin
, Jaan Raik
, Lembit Jürimägi
:
Fast identification of true critical paths in sequential circuits. Microelectron. Reliab. 81: 252-261 (2018) - [c135]Adeboye Stephen Oyeniran
, Siavoosh Payandeh Azad, Raimund Ubar
:
Combined pseudo-exhaustive and deterministic testing of array multipliers. AQTR 2018: 1-6 - [c134]Siavoosh Payandeh Azad, Adeboye Stephen Oyeniran
, Raimund Ubar
:
Replication-Based Deterministic Testing of 2-Dimensional Arrays with Highly Interrelated Cells. DDECS 2018: 21-26 - [c133]Adeboye Stephen Oyeniran
, Siavoosh Payandeh Azad, Raimund Ubar
:
Parallel Pseudo-Exhaustive Testing of Array Multipliers with Data-Controlled Segmentation. ISCAS 2018: 1-5 - [c132]Raimund Ubar
, Lembit Jurimagi
, Maksim Jenihhin
, Jaan Raik
, Niyi-Leigh Olugbenga, Vladimir Viies:
Timing-critical path analysis with structurally synthesized BDDs. MECO 2018: 1-6 - [c131]Jaak Kousaar, Raimund Ubar
, Sergei Kostin, Sergei Devadze
, Jaan Raik
:
Parallel Critical Path Tracing Fault Simulation in Sequential Circuits. MIXDES 2018: 305-310 - [c130]Lembit Jurimagi
, Raimund Ubar
, Maksim Jenihhin
, Jaan Raik
, Sergei Devadze
, Sergei Kostin:
Hierarchical Timing-Critical Paths Analysis in Sequential Circuits. PATMOS 2018: 1-6 - 2017
- [j27]Raimund Ubar
, Lembit Jürimägi
, Jaan Raik
, Vladimir Viies
:
Modeling and simulation of circuits with shared structurally synthesized BDDs. Microprocess. Microsystems 48: 56-61 (2017) - [c129]Siavoosh Payandeh Azad, Behrad Niazmand
, Karl Janson
, Nevin George, Stephen Adeboye Oyeniran
, Tsotne Putkaradze, Apneet Kaur, Jaan Raik
, Gert Jervan
, Raimund Ubar
, Thomas Hollstein
:
From online fault detection to fault management in Network-on-Chips: A ground-up approach. DDECS 2017: 48-53 - [c128]Raimund Ubar
, Sergei Kostin, Maksim Jenihhin
, Jaan Raik
:
A scalable technique to identify true critical paths in sequential circuits. DDECS 2017: 152-157 - [c127]Adeboye Stephen Oyeniran
, Artjom Jasnetski, Anton Tsertov
, Raimund Ubar
:
High-level test data generation for software-based self-test in microprocessors. MECO 2017: 1-6 - [c126]Artjom Jasnetski, Raimund Ubar
, Anton Tsertov
:
Automated software-based self-test generation for microprocessors. MIXDES 2017: 453-458 - [c125]Stephen Adeboye Oyeniran
, Raimund Ubar
, Siavoosh Payandeh Azad, Jaan Raik
:
High-level test generation for processing elements in many-core systems. ReCoSoC 2017: 1-8 - 2016
- [j26]Maksim Jenihhin
, Giovanni Squillero
, Thiago Santos Copetti, Valentin Tihhomirov, Sergei Kostin, Marco Gaudesi, Fabian Vargas, Jaan Raik
, Matteo Sonza Reorda
, Leticia Bolzani Poehls, Raimund Ubar
, Guilherme Cardoso Medeiros:
Identification and Rejuvenation of NBTI-Critical Logic Paths in Nanoscale Circuits. J. Electron. Test. 32(3): 273-289 (2016) - [c124]Raimund Ubar
, Stephen Adeboye Oyeniran
:
Multiple control fault testing in digital systems with high-level decision diagrams. AQTR 2016: 1-6 - [c123]Francesco Pellerey, Maksim Jenihhin
, Giovanni Squillero, Jaan Raik
, Matteo Sonza Reorda
, Valentin Tihhomirov, Raimund Ubar
:
Rejuvenation of NBTI-Impacted Processors Using Evolutionary Generation of Assembler Programs. ATS 2016: 304-309 - [c122]Artjom Jasnetski, Stephen Adeboye Oyeniran
, Anton Tsertov
, Mario Schölzel, Raimund Ubar
:
High-level modeling and testing of multiple control faults in digital systems. DDECS 2016: 144-149 - [c121]Sergei Kostin, Elmet Orasson, Raimund Ubar
:
A tool set for teaching design-for-testability of digital circuits. EWME 2016: 1-6 - [c120]Thiago Copetti, Guilherme Medeiros Machado, Leticia Bolzani Poehls, Fabian Vargas, Sergei Kostin, Maksim Jenihhin
, Jaan Raik
, Raimund Ubar
:
Gate-level modelling of NBTI-induced delays under process variations. LATS 2016: 75-80 - [c119]Artjom Jasnetski, Raimund Ubar
, Anton Tsertov
:
On automatic software-based self-test program generation based on high-level decision diagrams. LATS 2016: 177 - [c118]Emmanuel Ovie Osimiry, Raimund Ubar
, Sergei Kostin, Jaan Raik
:
A novel random approach to diagnostic test generation. NORCAS 2016: 1-4 - 2015
- [j25]Maksim Gorev, Raimund Ubar
, Peeter Ellervee
, Sergei Devadze
, Jaan Raik
, Mart Min:
Functional self-test of high-performance pipe-lined signal processing architectures. Microprocess. Microsystems 39(8): 909-918 (2015) - [j24]Jaak Kousaar, Raimund Ubar
, Sergei Devadze
, Jaan Raik
:
Transition delay fault simulation with parallel critical path back-tracing and 7-valued algebra. Microprocess. Microsystems 39(8): 1130-1138 (2015) - [c117]Maksim Gorev, Raimund Ubar, Sergei Devadze:
Fault simulation with parallel exact critical path tracing in multiple core environment. DATE 2015: 1180-1185 - [c116]Sergei Kostin, Jaan Raik
, Raimund Ubar
, Maksim Jenihhin
, Thiago Copetti, Fabian Vargas, Letícia Maria Bolzani Pöhls:
SPICE-Inspired Fast Gate-Level Computation of NBTI-induced Delays in Nanoscale Logic. DDECS 2015: 223-228 - [c115]Artjom Jasnetski, Jaan Raik
, Anton Tsertov
, Raimund Ubar
:
New Fault Models and Self-Test Generation for Microprocessors Using High-Level Decision Diagrams. DDECS 2015: 251-254 - [c114]Raimund Ubar
, Lembit Jurimagi
, Elmet Orasson, Galina Josifovska, Stephen Adeboye Oyeniran
:
Double Phase Fault Collapsing with Linear Complexity in Digital Circuits. DSD 2015: 700-705 - [c113]Raimund Ubar
, Stephen Adeboye Oyeniran
, Mario Schölzel, Heinrich Theodor Vierhaus:
Multiple fault testing in systems-on-chip with high-level decision diagrams. IDT 2015: 66-71 - [c112]Raimund Ubar
, Jaak Kousaar, Maksim Gorev, Sergei Devadze
:
Combinational fault simulation in sequential circuits. ISCAS 2015: 2876-2879 - [c111]Jaak Kousaar, Raimund Ubar
, Igor Aleksejev
:
Complex delay fault reasoning with sequential 7-valued algebra. LATS 2015: 1-6 - [c110]Raimund Ubar
, Lembit Jurimagi
, Jaan Raik
:
Shared Structurally Synthesized BDDs for speeding-up parallel pattern simulation in digital circuits. NORCAS 2015: 1-4 - [c109]Raimund Ubar
, Lembit Jürimägi
, Elmet Orasson, Jaan Raik
:
Fault Collapsing in Digital Circuits Using Fast Fault Dominance and Equivalence Analysis with SSBDDs. VLSI-SoC (Selected Papers) 2015: 23-45 - [c108]Raimund Ubar
, Lembit Jurimagi
, Elmet Orasson, Jaan Raik
:
Scalable algorithm for structural fault collapsing in digital circuits. VLSI-SoC 2015: 171-176 - 2014
- [j23]Maksim Jenihhin
, Anton Tsepurov, Valentin Tihhomirov, Jaan Raik
, Hanno Hantson, Raimund Ubar
, Gunter Bartsch, Jorge Hernán Meza Escobar, Heinz-Dietrich Wuttke
:
Automated Design Error Localization in RTL Designs. IEEE Des. Test 31(1): 83-92 (2014) - [c107]Raimund Ubar
, Dmitri Mironov
:
Lower bounds of the size of Shared Structurally Synthesized BDDs. DDECS 2014: 77-82 - [c106]Jaak Kousaar, Raimund Ubar
, Sergei Devadze
, Jaan Raik
:
Critical Path Tracing Based Simulation of Transition Delay Faults. DSD 2014: 108-113 - [c105]Dmitri Mironov
, Raimund Ubar
, Jaan Raik
:
Logic simulation and fault collapsing with shared structurally synthesized bdds. ETS 2014: 1-2 - [c104]Marco Gaudesi, Maksim Jenihhin
, Jaan Raik
, Ernesto Sánchez, Giovanni Squillero, Valentin Tihhomirov, Raimund Ubar
:
Diagnostic Test Generation for Statistical Bug Localization Using Evolutionary Computation. EvoApplications 2014: 425-436 - [c103]Artjom Jasnetski, Raimund Ubar
, Anton Tsertov
, Helena Kruus:
Laboratory framework TEAM for investigating the dependability issues of microprocessor systems. EWME 2014: 80-83 - [c102]Heinrich Theodor Vierhaus, Mario Schölzel, Jaan Raik
, Raimund Ubar
:
Advanced technical education in the age of cyber physical systems. EWME 2014: 193-198 - [c101]Raimund Ubar
, Mihhail Marenkov, Dmitri Mironov
, Vladimir Viies:
Modeling sequential circuits with shared structurally synthesized BDDs. IDT 2014: 130-135 - [c100]Sergei Kostin, Jaan Raik
, Raimund Ubar
, Maksim Jenihhin
, Fabian Vargas, Letícia Maria Bolzani Poehls, Thiago Santos Copetti:
Hierarchical identification of NBTI-critical gates in nanoscale logic. LATW 2014: 1-6 - [c99]Raimund Ubar
, Anton Tsertov
, Artjom Jasnetski, Marina Brik:
Software-based self-test generation for microprocessors with high-level decision diagrams. LATW 2014: 1-6 - 2013
- [j22]Jaan Raik
, Urmas Repinski, Anton Chepurov, Hanno Hantson, Raimund Ubar
, Maksim Jenihhin
:
Automated design error debug using high-level decision diagrams and mutation operators. Microprocess. Microsystems 37(4-5): 505-513 (2013) - [j21]Ivo Fridolin
, Deniss Karai, Sergei Kostin, Raimund Ubar
:
Accurate Dialysis Dose Evaluation and Extrapolation Algorithms During Online Optical Dialysis Monitoring. IEEE Trans. Biomed. Eng. 60(5): 1371-1377 (2013) - [c98]Raimund Ubar
, Fabian Vargas, Maksim Jenihhin
, Jaan Raik
, Sergei Kostin, Letícia Maria Bolzani Poehls:
Identifying NBTI-Critical Paths in Nanoscale Logic. DSD 2013: 136-141 - [c97]Raimund Ubar
, Sergei Kostin, Jaan Raik
:
Synthesis of multiple fault oriented test groups from single fault test sets. DTIS 2013: 98-103 - [c96]Valentin Tihhomirov, Anton Tsepurov, Maksim Jenihhin
, Jaan Raik
, Raimund Ubar
:
Assessment of diagnostic test for automated bug localization. LATW 2013: 1-6 - [c95]Raimund Ubar
:
Diagnostic modeling of digital systems with low- and high-level decision diagrams. LATW 2013: 1 - [c94]Maksim Gorev, Raimund Ubar
, Peeter Ellervee
, Sergei Devadze
, Jaan Raik
, Mart Min:
At-speed self-testing of high-performance pipe-lined processing architectures. NORCHIP 2013: 1-6 - 2012
- [j20]Valerio Guarnieri, Giuseppe Di Guglielmo, Nicola Bombieri
, Graziano Pravadelli
, Franco Fummi, Hanno Hantson, Jaan Raik
, Maksim Jenihhin
, Raimund Ubar
:
On the Reuse of TLM Mutation Analysis at RTL. J. Electron. Test. 28(4): 435-448 (2012) - [j19]Taavi Viilukas, Anton Karputkin, Jaan Raik
, Maksim Jenihhin
, Raimund Ubar
, Hideo Fujiwara:
Identifying Untestable Faults in Sequential Circuits Using Test Path Constraints. J. Electron. Test. 28(4): 511-521 (2012) - [c93]Raimund Ubar
, Sergei Kostin, Jaan Raik
:
Multiple stuck-at-fault detection theorem. DDECS 2012: 236-241 - [c92]Raimund Ubar
, Sergei Kostin, Jaan Raik
:
How to Prove that a Circuit is Fault-Free? DSD 2012: 427-430 - [c91]Urmas Repinski, Hanno Hantson, Maksim Jenihhin
, Jaan Raik
, Raimund Ubar
, Giuseppe Di Guglielmo, Graziano Pravadelli
, Franco Fummi:
Combining dynamic slicing and mutation operators for ESL correction. ETS 2012: 1-6 - [c90]Anton Karputkin, Raimund Ubar
, Mati Tombak, Jaan Raik
:
Automated correction of design errors by edge redirection on High-Level Decision Diagrams. ISQED 2012: 686-693 - [c89]Hanno Hantson, Urmas Repinski, Jaan Raik
, Maksim Jenihhin
, Raimund Ubar
:
Diagnosis and correction of multiple design errors using critical path tracing and mutation analysis. LATW 2012: 1-6 - [c88]Raimund Ubar
, Sergei Kostin, Jaan Raik
:
About robustness of test patterns regarding multiple faults. LATW 2012: 1-6 - [c87]Raimund Ubar
, Viljar Indus, Oliver Kalmend, Teet Evartson, Elmet Orasson:
Functional Built-In Self-Test for processor cores in SoC. NORCHIP 2012: 1-4 - [e2]Jaan Raik, Viera Stopjaková, Heinrich Theodor Vierhaus, Witold A. Pleskacz, Raimund Ubar, Helena Kruus, Maksim Jenihhin:
IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2012, Tallinn, Estonia, April 18-20, 2012. IEEE 2012, ISBN 978-1-4673-1187-8 [contents] - 2011
- [j18]Eero Ivask, Sergei Devadze, Raimund Ubar:
Distributed Fault Simulation with Collaborative Load Balancing for VLSI Circuits. Scalable Comput. Pract. Exp. 12(1) (2011) - [c86]Anton Tsertov
, Raimund Ubar
, Artur Jutman
, Sergei Devadze
:
Automatic SoC Level Test Path Synthesis Based on Partial Functional Models. Asian Test Symposium 2011: 532-538 - [c85]Sergei Kostin, Raimund Ubar
, Jaan Raik
:
Defect-oriented module-level fault diagnosis in digital circuits. DDECS 2011: 81-86 - [c84]Anton Karputkin, Raimund Ubar
, Mati Tombak, Jaan Raik
:
Probabilistic equivalence checking based on high-level decision diagrams. DDECS 2011: 423-428 - [c83]Uljana Reinsalu, Jaan Raik
, Raimund Ubar
, Peeter Ellervee
:
Fast RTL Fault Simulation Using Decision Diagrams and Bitwise Set Operations. DFT 2011: 164-170 - [c82]Anton Tsertov
, Raimund Ubar
, Artur Jutman
, Sergei Devadze
:
SoC and Board Modeling for Processor-Centric Board Testing. DSD 2011: 575-582 - [c81]Jaan Raik
, Anna Rannaste, Maksim Jenihhin
, Taavi Viilukas, Raimund Ubar
, Hideo Fujiwara:
Constraint-Based Hierarchical Untestability Identification for Synchronous Sequential Circuits. ETS 2011: 147-152 - [c80]Taavi Viilukas, Maksim Jenihhin
, Jaan Raik
, Raimund Ubar
, Samary Baranov:
Automated test bench generation for high-level synthesis flow ABELITE. EWDTS 2011: 13-16 - [c79]Anton Karputkin, Raimund Ubar, Mati Tombak, Jaan Raik:
Interactive presentation abstract: Automated correction of design errors by edge redirection on high-level decision diagrams. HLDVT 2011: 83 - [c78]Valerio Guarnieri, Nicola Bombieri
, Graziano Pravadelli
, Franco Fummi, Hanno Hantson, Jaan Raik
, Maksim Jenihhin
, Raimund Ubar
:
Mutation analysis for SystemC designs at TLM. LATW 2011: 1-6 - 2010
- [c77]Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman:
Parallel X-fault simulation with critical path tracing technique. DATE 2010: 879-884 - [c76]Taavi Viilukas, Jaan Raik
, Maksim Jenihhin
, Raimund Ubar
, Anna Krivenko:
Constraint-based test pattern generation at the Register-Transfer Level. DDECS 2010: 352-357 - [c75]Raimund Ubar
, Sergei Devadze
, Jaan Raik
, Artur Jutman
:
Fast Fault Simulation for Extended Class of Faults in Scan Path Circuits. DELTA 2010: 14-19 - [c74]Dmitri Mironov
, Raimund Ubar
, Sergei Devadze
, Jaan Raik
, Artur Jutman
:
Structurally Synthesized Multiple Input BDDs for Speeding Up Logic-Level Simulation of Digital Circuits. DSD 2010: 658-663 - [c73]Maksim Jenihhin
, Jaan Raik
, Raimund Ubar
, Tatjana Shchenova:
An approach for PSL assertion coverage analysis with high-level decision diagrams. EWDTS 2010: 13-16 - [c72]Eero Ivask, Sergei Devadze
, Raimund Ubar
:
Collaborative Distributed Fault Simulation for Digital Electronic Circuits. IDC 2010: 67-76 - [c71]Eero Ivask, Sergei Devadze
, Raimund Ubar
:
Collaborative Distributed Computing in the Field of Digital Electronics Testing. BASYS 2010: 145-152 - [c70]Raimund Ubar
, Dmitri Mironov
, Jaan Raik
, Artur Jutman
:
Fault collapsing with linear complexity in digital circuits. ISCAS 2010: 653-656 - [c69]Heinz-Dietrich Wuttke
, Raimund Ubar
, Karsten Henke
:
Remote and Virtual Laboratories in Problem-Based Learning Scenarios. ISM 2010: 377-382 - [c68]Raimund Ubar
, Dmitri Mironov
, Jaan Raik
, Artur Jutman
:
Structural fault collapsing by superposition of BDDs for test generation in digital circuits. ISQED 2010: 250-257 - [c67]Hanno Hantson, Jaan Raik
, Maksim Jenihhin
, Anton Chepurov, Raimund Ubar
, Giuseppe Di Guglielmo, Franco Fummi:
Mutation analysis with high-level decision diagrams. LATW 2010: 1-6 - [i1]Yuriy A. Skobtsov, D. E. Ivanov, V. Y. Skobtsov, Raimund Ubar, Jaan Raik:
Evolutionary Approach to Test Generation for Functional BIST. CoRR abs/1008.0063 (2010)
2000 – 2009
- 2009
- [j17]Maksim Jenihhin
, Jaan Raik
, Anton Chepurov, Raimund Ubar
:
PSL Assertion Checking Using Temporally Extended High-Level Decision Diagrams. J. Electron. Test. 25(6): 289-300 (2009) - [j16]Jaan Raik
, Vineeth Govind, Raimund Ubar
:
Design-for-testability-based external test and diagnosis of mesh-like network-on-a-chips. IET Comput. Digit. Tech. 3(5): 476-486 (2009) - [c66]Raimund Ubar
, Sergei Kostin, Jaan Raik
:
Block-Level Fault Model-Free Debug and Diagnosis in Digital Systems. DSD 2009: 229-232 - [c65]Raimund Ubar
, Dmitri Mironov
, Jaan Raik
, Artur Jutman
:
Structurally synthesized multiple input BDDs for simulation of digital circuits. ICECS 2009: 451-454 - [c64]Sergei Devadze
, Artur Jutman
, Igor Aleksejev
, Raimund Ubar
:
Fast extended test access via JTAG and FPGAs. ITC 2009: 1-7 - [c63]Sergei Devadze
, Artur Jutman
, Igor Aleksejev
, Raimund Ubar
:
Turning JTAG inside out for fast extended test access. LATW 2009: 1-6 - [c62]Maksim Jenihhin
, Jaan Raik
, Anton Chepurov, Uljana Reinsalu, Raimund Ubar
:
High-Level Decision Diagrams based coverage metrics for verification and test. LATW 2009: 1-6 - [c61]Raimund Ubar
, Sergei Kostin, Jaan Raik
:
Investigations of the diagnosibility of digital networks with BIST. LATW 2009: 1-6 - [c60]Raimund Ubar
, Artur Jutman
, Jaan Raik
, Sergei Kostin, Heinz-Dietrich Wuttke
:
Diagnozer: A laboratory tool for teaching research in diagnosis of electronic systems. MSE 2009: 12-15 - 2008
- [j15]Tomas Bengtsson, Shashi Kumar, Raimund Ubar
, Artur Jutman
, Zebo Peng:
Test methods for crosstalk-induced delay and glitch faults in network-on-chip interconnects implementing asynchronous communication protocols. IET Comput. Digit. Tech. 2(6): 445-460 (2008) - [j14]Jaan Raik
, Raimund Ubar
, Taavi Viilukas, Maksim Jenihhin
:
Mixed hierarchical-functional fault models for targeting sequential cores. J. Syst. Archit. 54(3-4): 465-477 (2008) - [j13]