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ORCID9. FPGA 2001: Monterey, CA, USA
- Scott Hauck, Martine D. F. Schlag, Russell Tessier:
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2001, Monterey, CA, USA, February 11-13, 2001. ACM 2001, ISBN 1-58113-341-3 - K. K. Lee, D. F. Wong
:
LRoute: a delay minimal router for hierarchical CPLDs. 12-20 - Steven J. E. Wilton:
A crosstalk-aware timing-driven router for FPGAs. 21-28 - Chandra Mulpuri, Scott Hauck:
Runtime and quality tradeoffs in FPGA placement and routing. 29-36 - Deming Chen, Jason Cong, Milos D. Ercegovac, Zhijun Huang:
Performance-driven mapping for CPLD architectures. 39-47 - Gang Chen, Jason Cong:
Simultaneous logic decomposition with technology mapping in FPGA designs. 48-55 - Guy G. Lemieux, David M. Lewis:
Using sparse crossbars within LUT. 59-68 - Peter Hallschmid, Steven J. E. Wilton:
Detailed routing architectures for embedded programmable logic IP cores. 69-74 - Mike Sheng, Jonathan Rose:
Mixing buffers and pass transistors in FPGA routing architectures. 75-84 - John W. Lockwood, Naji Naufel, Jonathan S. Turner, David E. Taylor:
Reprogrammable network packet processing on the field programmable port extender (FPX). 87-93 - Pawel Chodowiec, Po Khuon, Kris Gaj:
Fast implementations of secret-key block ciphers using mixed inner- and outer-round pipelining. 94-102 - Mike Estlick, Miriam Leeser, James Theiler, John J. Szymanski:
Algorithmic transformations in the implementation of K- means clustering on reconfigurable hardware. 103-110 - Sinan Kaptanoglu, John East, Tim Garverick, Scott Hauck, Tavana Tavana, Steven Trimberger, Ronnie Vasishta:
Is marriage in the cards for programmable logic, microprocessors and ASICs? 111 - Greg Snider, Barry Shackleford, Richard J. Carter:
Attacking the semantic gap between application programming languages and configurable hardware. 115-124 - Pablo Moisset, Pedro C. Diniz, Joonseok Park:
Matching and searching analysis for parallel hardware implementation on FPGAs. 125-133 - Janette Frigo, Maya B. Gokhale, Dominique Lavenier:
Evaluation of the streams-C C-to-FPGA compiler: an applications perspective. 134-140 - Jorge E. Carrillo, Paul Chow:
The effect of reconfigurable units in superscalar processors. 141-150 - Amit Singh, Arindam Mukherjee, Malgorzata Marek-Sadowska:
Interconnect pipelining in a throughput-intensive FPGA architecture. 153-160 - Deshanand P. Singh, Stephen Dean Brown:
The case for registered routing switches in field programmable gate arrays. 161-169 - Andreas Dandalis, Viktor K. Prasanna:
Configuration compression for FPGA-based embedded systems. 173-182 - Wei-Je Huang, Edward J. McCluskey:
A memory coherence technique for online transient error recovery of FPGA configurations. 183-192 - Prasanna Sundararajan, Steve Guccione:
Run-Time defect tolerance using JBits. 193-198 - Jörg Ritter, Paul Molitor:
A pipelined architecture for partitioned DWT based lossy image compression using FPGA's. 201-206 - Gerhard Lienhart, Reinhard Männer, Klaus-Henning Noffz, Ralf Lay:
An FPGA-based video compressor for H.263 compatible bit streams. 207-212 - Seetharaman Ramachandran, S. Srinivasan:
FPGA implementation of a novel, fast motion estimation algorithm for real-time video compression. 213-219
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