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ORCID4. Great Lakes Symposium on VLSI 1994: Notre Dame, IN, USA
- Fourth Great Lakes Symposium on Design Automation of High Performance VLSI Systems, GLSV '94, Notre Dame, IN, USA, March 4-5, 1994. IEEE 1994, ISBN 0-8186-5610-7
- M. Vashi, Vijay K. Raj, Hee Yong Youn:
A distributed controller for system level integration. 2-5 - Liang-Fang Chao:
Optimizing cyclic data-flow graphs via associativity. 6-10 - Yatin Vasant Hoskote, John Moondanos, Jacob A. Abraham, Donald S. Fussell:
Abstraction of data path registers for multilevel verification of large circuits. 11-14 - Raghava V. Cherabuddi, Magdy A. Bayoumi:
Automated system partitioning for synthesis of multi-chip modules. 15-20 - Maurizio Rebaudengo, Matteo Sonza Reorda
:
Floorplan area optimization using genetic algorithms. 22-25 - Arun Shanbhag, Srinivasa R. Danda, Naveed A. Sherwani:
Floorplanning for mixed macro block and standard cell designs. 26-29 - Chi-Yu Mao, Yu Hen Hu:
Convergence analyses of simulated evolution algorithms. 30-33 - Dinesh P. Mehta:
Estimating the storage requirements of the rectangular and L-shaped corner stitching data structures. 34-37 - Stanislav G. Sedukhin:
A new systolic architecture for pipeline prime factor DFT-algorithm. 40-45 - Jermy C. Smith, Fred J. Taylor:
The design of a fault tolerant GEQRNS processing element for linear systolic array DSP applications. 46-49 - Hung-Kuei Ku, John P. Hayes:
Structural fault tolerance in VLSI-based systems. 50-55 - Chin-Chien Sha, R. W. Leavene:
An algorithm-base fault tolerance (more than one error) using concurrent error detection for FFT processors. 56-61 - V. Shankar, Dinesh Bhatia:
Generalized segmented channel routing. 64-69 - Yu-Liang Wu, Shuji Tsukiyama, Malgorzata Marek-Sadowska:
On computational complexity of a detailed routing problem in two dimensional FPGAs. 70-75 - Dinesh Bhatia, Amit Chowdhary, Spyros Tragoudas:
Mathematical model for routability analysis of FPGAs. 76-79 - Anand Panyam, Srinivasa R. Danda, Sreekrishna Madhwapathy, Naveed A. Sherwani:
An optimal algorithm for maximum two planar subset problem [VLSI layout]. 80-85 - Yulin Chen, Wei Kang Tsai, Fadi J. Kurdahi, Tzong-Dar Her, Champaka Ramachandran:
A performance driven logic synthesis system using delay estimator. 88-92 - Gianpiero Cabodi, Paolo Camurati, Stefano Quer:
Symbolic traversals of data paths with auxiliary variables. 93-96 - Wen-Lin Yang, Robert Michael Owens, Mary Jane Irwin:
FPGA-based synthesis of FSMs through decomposition. 97-100 - Paul Molitor, Christoph Scholl:
Communication based multilevel synthesis for multi-output Boolean functions. 101-104 - Jawahar Jain, James R. Bitner, Dinos Moundanos, Jacob A. Abraham, Donald S. Fussell:
A new scheme to compute variable orders for binary decision diagrams. 105-108 - Atul Garg, James Loy, Hans J. Greub, John F. McDonald:
Design of a package for a high-speed processor made with yield-limited technology. 110-113 - Douglas Chang, Teofilo F. Gonzalez, Oscar H. Ibarra:
A flow based approach to the pin redistribution problem for multi-chip modules. 114-119 - James Loy, Atul Garg, Mukkai S. Krishnamoorthy, John F. McDonald:
Wiring pitch integrates MCM design domains. 120-123 - José G. Delgado-Frias, Rovy Sze, Douglas H. Summerville, Valentine C. Aikens II:
A VLSI CAM-based flexible oblivious router for multiprocessor interconnection networks. 124-129 - Henk Corporaal:
Design of transport triggered architectures. 130-135 - Richard R. Schultz, H. M. Zeyedt, Robert L. Stevenson, R. J. Minniti, C. H. Bernstein:
ASIC design for robust signal and image processing. 138-143 - Jeong-A Lee, Mubashir Ahmad:
VLSI implementation of CORDIC angle units. 144-149 - Ayman Elnaggar, Hussein M. Alnuweiri, Mabo Robert Ito:
Mapping tensor products onto VLSI networks with reduced I/O. 150-155 - Naresh Sehgal, C. Y. Roger Chen, John M. Acken:
A gridless multi-layer area router. 158-161 - Jin-Tai Yan, Pei-Yung Hsiao:
Routability crossing distribution and floating terminal assignment of T-type junction region. 162-165 - Ramesh Karri, Alex Orailoglu:
Simulated annealing based yield enhancement of layouts. 166-169 - Hon Fung Li, S. C. Leung:
An efficient algorithm for the realizability analysis of signal transition graphs. 174-179 - Mehmet Emin Dalkiliç, Vijay Pitchumani:
Distributed data-path synthesis on a network of workstations. 180-183 - Ivailo M. Nedelchev, Chris R. Jesshope:
Basic building blocks for asynchronous packet routers. 184-187 - Yu Hen Hu, Duen-Jeng Wang:
An efficient multiprocessor implementation scheme for real-time DSP algorithms. 188-193 - William C. Athas, Jefferey G. Koller, Lars J. Svensson:
An energy-efficient CMOS line driver using adiabatic switching. 196-199 - Srinivasa Vemuru:
Scaling of serially-connected MOSFET chains. 200-203 - Reza Hashemian:
Design of a 54-bit adder using a modified Manchester carry chain. 204-207 - Khaled M. Sharaf, Mohamed I. Elmasry:
Low-power differential CML and ECL BiCMOS circuit techniques. 208-213 - Dimitrios Kagaris, Spyros Tragoudas:
Retiming algorithms with application to VLSI testability. 216-221 - Bhanu Kapoor, V. S. S. Nair:
Area, performance, and sensitizable paths [logic design]. 222-227 - Tapan J. Chakraborty, Vishwani D. Agrawal:
Delay independent initialization of sequential circuits. 228-230 - Jalal A. Wehbeh, Daniel G. Saab:
Efficient simulation of switch-level circuits in a hierarchical simulation environment. 231-235 - Joseph L. Ganley, James P. Cohoon:
A faster dynamic programming algorithm for exact rectilinear Steiner minimal trees. 238-241 - Spyros Tragoudas:
An improved algorithm for the generalized min-cut partitioning problem. 242-247 - R. Iris Bahar, Gary D. Hachtel, Abelardo Pardo, Massimo Poncino, Fabio Somenzi:
An ADD-based algorithm for shortest path back-tracing of large graphs. 248-251 - Qicheng Yu, Carl Sechen:
Generation of color-constrained spanning trees with application in symbolic circuit analysis. 252-255
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