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ORCIDJohn P. Hayes
John Patrick Hayes
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- affiliation: University of Michigan, Ann Arbor, USA
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2020 – today
- 2024
[c145]Roshwin Sengupta, Ilia Polian, John P. Hayes:
Performance and Error Tolerance of Stochastic Computing-Based Digital Filter Design. DDECS 2024: 7-12- 2023
- [c144]Timothy J. Baker, John P. Hayes:
Design of Large-Scale Stochastic Computing Adders and their Anomalous Behavior. DATE 2023: 1-6 - [c143]Florian Neugebauer, Vivek Vekariya, Ilia Polian, John P. Hayes:
Stochastic Computing as a Defence Against Adversarial Attacks. DSN-W 2023: 191-194 - [c142]Owen Hoffend, John P. Hayes:
Mitigating the Correlation Problem in Multi-Layer Stochastic Circuits. ICRC 2023: 1-10 - 2022
- [j113]Timothy J. Baker
, John P. Hayes:
CeMux: Maximizing the Accuracy of Stochastic Mux Adders and an Application to Filter Design. ACM Trans. Design Autom. Electr. Syst. 27(3): 27:1-27:26 (2022) - [c141]Roshwin Sengupta, Ilia Polian, John P. Hayes:
Stochastic Computing Architectures for Lightweight LSTM Neural Networks. DDECS 2022: 124-129 - [c140]Owen Hoffend, John P. Hayes:
Analyzing Multilevel Stochastic Circuits using Correlation Matrices. DDECS 2022: 130-135 - [c139]Roshwin Sengupta, Ilia Polian, John P. Hayes:
Wavelet Transform Assisted Neural Networks for Human Activity Recognition. ISCAS 2022: 1254-1258 - [c138]Timothy J. Baker, Owen Hoffend, John P. Hayes:
Multiplexer-Majority Chains: Managing Correlation and Cost in Stochastic Number Generation. NANOARCH 2022: 21:1-21:6 - 2021
- [j112]Ilia Polian, John P. Hayes, Vincent T. Lee, Weikang Qian:
Guest Editors' Introduction: Stochastic Computing for Neuromorphic Applications. IEEE Des. Test 38(6): 5-15 (2021) - [c137]Timothy J. Baker, Yiqiu Sun, John P. Hayes:
Benefits of Stochastic Computing in Hearing Aid Filterbank Design. BioCAS 2021: 1-5 - [i3]Timothy J. Baker, John P. Hayes:
CeMux: Maximizing the Accuracy of Stochastic Mux Adders and an Application to Filter Design. CoRR abs/2108.12326 (2021) - 2020
- [c136]Timothy J. Baker, John P. Hayes:
The Hypergeometric Distribution as a More Accurate Model for Stochastic Computing. DATE 2020: 592-597 - [c135]Chen Wang, Weihua Xiao, John P. Hayes, Weikang Qian:
Exploring Target Function Approximation for Stochastic Circuit Minimization. ICCAD 2020: 122:1-122:9 - [c134]Timothy J. Baker, John P. Hayes:
Bayesian Accuracy Analysis of Stochastic Circuits. ICCAD 2020: 124:1-124:9 - [c133]Ponnanna Kelettira Muthappa, Florian Neugebauer, Ilia Polian, John P. Hayes:
Hardware-based Fast Real-time Image Classification with Stochastic Computing. ICCD 2020: 340-347 - [c132]Junseok Oh, Florian Neugebauer, Ilia Polian, John P. Hayes:
Retraining and Regularization to Optimize Neural Networks for Stochastic Computing. ISVLSI 2020: 246-251
2010 – 2019
- 2019
- [j111]Pai-Shun Ting, John P. Hayes:
Removing constant-induced errors in stochastic circuits. IET Comput. Digit. Tech. 13(3): 187-197 (2019) - [j110]Te-Hsuan Chen, John P. Hayes:
Equivalence Among Stochastic Logic Circuits and its Application to Synthesis. IEEE Trans. Emerg. Top. Comput. 7(1): 67-79 (2019) - [c131]Florian Neugebauer, Ilia Polian, John P. Hayes:
On the maximum function in stochastic computing. CF 2019: 59-66 - [c130]Pai-Shun Ting, John P. Hayes:
Exploiting Randomness in Stochastic Computing. ICCAD 2019: 1-6 - [c129]Florian Neugebauer, Ilia Polian, John P. Hayes:
On the Limits of Stochastic Computing. ICRC 2019: 98-105 - [c128]Timothy J. Baker, John P. Hayes:
Impact of Autocorrelation on Stochastic Circuit Accuracy. ISVLSI 2019: 271-277 - 2018
- [j109]Dinesh A. Mirchandani, Yunus Kathawala, Julius H. Johnson Jr., John P. Hayes, Sudhir Chawla:
A comparison of perspectives of Kuwaiti and Indonesian residents towards e-government. Electron. Gov. an Int. J. 14(2): 134-159 (2018) - [j108]Florian Neugebauer, Ilia Polian, John P. Hayes:
Framework for Quantifying and Managing Accuracy in Stochastic Circuit Design. ACM J. Emerg. Technol. Comput. Syst. 14(2): 31:1-31:21 (2018) - [j107]Florian Neugebauer, Ilia Polian, John P. Hayes:
S-box-based random number generation for stochastic computing. Microprocess. Microsystems 61: 316-326 (2018) - [j106]Armin Alaghi, Weikang Qian, John P. Hayes:
The Promise and Challenge of Stochastic Computing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(8): 1515-1531 (2018) - [c127]Pai-Shun Ting, John P. Hayes:
Maxflow: Minimizing Latency in Hybrid Stochastic-Binary Systems. ACM Great Lakes Symposium on VLSI 2018: 21-26 - 2017
- [j105]Armin Alaghi, Wei-Ting Jonas Chan, John P. Hayes, Andrew B. Kahng, Jiajia Li:
Trading Accuracy for Energy in Stochastic Circuit Design. ACM J. Emerg. Technol. Comput. Syst. 13(3): 47:1-47:30 (2017) - [c126]Florian Neugebauer, Ilia Polian, John P. Hayes:
Framework for quantifying and managing accuracy in stochastic circuit design. DATE 2017: 1-6 - [c125]Vincent T. Lee, Armin Alaghi, John P. Hayes, Visvesh Sathe, Luis Ceze:
Energy-efficient hybrid stochastic-binary neural networks for near-sensor computing. DATE 2017: 13-18 - [c124]Pai-Shun Ting, John P. Hayes:
Eliminating a hidden error source in stochastic circuits. DFT 2017: 1-6 - [c123]Florian Neugebauer, Ilia Polian, John P. Hayes:
Building a Better Random Number Generator for Stochastic Computing. DSD 2017: 1-8 - [c122]Te-Hsuan Chen, Pai-Shun Ting, John P. Hayes:
Achieving progressive precision in stochastic computing. GlobalSIP 2017: 1320-1324 - [c121]Pai-Shun Ting, John P. Hayes:
On the Role of Sequential Circuits in Stochastic Computing. ACM Great Lakes Symposium on VLSI 2017: 475-478 - [c120]Meng Yang, John P. Hayes, Deliang Fan, Weikang Qian:
Design of accurate stochastic number generators with noisy emerging devices for stochastic computing. ICCAD 2017: 638-644 - [i2]Vincent T. Lee, Armin Alaghi, John P. Hayes, Visvesh Sathe, Luis Ceze:
Energy-Efficient Hybrid Stochastic-Binary Neural Networks for Near-Sensor Computing. CoRR abs/1706.02344 (2017) - 2016
- [c119]Pai-Shun Ting, John P. Hayes:
Isolation-based decorrelation of stochastic circuits. ICCD 2016: 88-95 - [c118]Te-Hsuan Chen, John P. Hayes:
Design of Division Circuits for Stochastic Computing. ISVLSI 2016: 116-121 - 2015
- [j104]Armin Alaghi, John P. Hayes:
STRAUSS: Spectral Transform Use in Stochastic Circuit Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(11): 1770-1783 (2015) - [c117]John P. Hayes:
Introduction to stochastic computing and its challenges. DAC 2015: 59:1-59:3 - [c116]Te-Hsuan Chen, John P. Hayes:
Equivalence among stochastic logic circuits and its application. DAC 2015: 131:1-131:6 - [c115]I-Che Chen, John P. Hayes:
Low-Area and High-Speed Approximate Matrix-Vector Multiplier. DDECS 2015: 23-28 - [c114]Armin Alaghi, John P. Hayes:
On the Functions Realized by Stochastic Computing Circuits. ACM Great Lakes Symposium on VLSI 2015: 331-336 - [c113]Armin Alaghi, Wei-Ting Jonas Chan, John P. Hayes, Andrew B. Kahng, Jiajia Li:
Optimizing Stochastic Circuits for Accuracy-Energy Tradeoffs. ICCAD 2015: 178-185 - [c112]Armin Alaghi, John P. Hayes:
Dimension reduction in statistical simulation of digital circuits. SpringSim (TMS-DEVS) 2015: 1-8 - 2014
- [j103]Te-Hsuan Chen, Armin Alaghi, John P. Hayes:
Behavior of stochastic circuits under severe error conditions. it Inf. Technol. 56(4): 182-191 (2014) - [c111]Armin Alaghi, John P. Hayes:
Fast and accurate computation using stochastic circuits. DATE 2014: 1-4 - [c110]Pai-Shun Ting, John Patrick Hayes:
Stochastic Logic Realization of Matrix Operations. DSD 2014: 356-364 - [c109]Te-Hsuan Chen, John P. Hayes:
Analyzing and controlling accuracy in stochastic circuits. ICCD 2014: 367-373 - 2013
- [b3]Smita Krishnaswamy, Igor L. Markov, John P. Hayes:
Design, Analysis and Test of Logic Circuits Under Uncertainty. Lecture Notes in Electrical Engineering 115, Springer 2013, ISBN 978-90-481-9643-2, pp. 1-120 - [j102]Armin Alaghi, John P. Hayes:
Survey of Stochastic Computing. ACM Trans. Embed. Comput. Syst. 12(2s): 92:1-92:19 (2013) - [c108]Armin Alaghi, Cheng Li, John P. Hayes:
Stochastic circuits for real-time image-processing applications. DAC 2013: 136:1-136:6 - [c107]Te-Hsuan Chen, John P. Hayes:
Design of stochastic Viterbi decoders for convolutional codes. DDECS 2013: 66-71 - [c106]Alexandru Paler, Josef Kinseher, Ilia Polian, John P. Hayes:
Approximate simulation of circuits with probabilistic behavior. DFTS 2013: 95-100 - [c105]Armin Alaghi, John P. Hayes:
Exploiting correlation in stochastic circuit design. ICCD 2013: 39-46 - 2012
- [j101]Joonhwan Yi, John P. Hayes:
Robust Coupling Delay Test Sets. J. Electron. Test. 28(3): 375-388 (2012) - [j100]Kenneth M. Zick, John P. Hayes:
Low-cost sensing with ring oscillator arrays for healthier reconfigurable systems. ACM Trans. Reconfigurable Technol. Syst. 5(1): 1:1-1:26 (2012) - [c104]Alexandru Paler, Ilia Polian, John P. Hayes:
Detection and diagnosis of faulty quantum circuits. ASP-DAC 2012: 181-186 - [c103]Chien-Chih Yu, Armin Alaghi, John P. Hayes:
Scalable sampling methodology for logic simulation: Reduced-Ordered Monte Carlo. ICCAD 2012: 195-201 - [c102]Armin Alaghi, John P. Hayes:
A spectral transform approach to stochastic circuits. ICCD 2012: 315-321 - 2011
- [j99]Ilia Polian, John P. Hayes:
Selective Hardening: Toward Cost-Effective Error Tolerance. IEEE Des. Test Comput. 28(3): 54-63 (2011) - [j98]Ilia Polian, John P. Hayes, Sudhakar M. Reddy, Bernd Becker:
Modeling and Mitigating Transient Errors in Logic Circuits. IEEE Trans. Dependable Secur. Comput. 8(4): 537-547 (2011) - [c101]Dae Young Lee, David D. Wentzloff, John P. Hayes:
A 900 Mbps single-channel capacitive I/O link for wireless wafer-level testing of integrated circuits. A-SSCC 2011: 153-156 - [c100]Chien-Chih Yu, John P. Hayes:
Trigonometric method to handle realistic error probabilities in logic circuits. DATE 2011: 64-69 - [c99]Dae Young Lee, David D. Wentzloff, John P. Hayes:
Wireless wafer-level testing of integrated circuits via capacitively-coupled channels. DDECS 2011: 99-104 - [c98]Alexandru Paler, Armin Alaghi, Ilia Polian, John P. Hayes:
Tomographic Testing and Validation of Probabilistic Circuits. ETS 2011: 63-68 - 2010
- [c97]Ilia Polian, John P. Hayes:
Advanced modeling of faults in Reversible circuits. EWDTS 2010: 376-381 - [c96]Kenneth M. Zick, John P. Hayes:
On-line sensing for healthier FPGA systems. FPGA 2010: 239-248 - [c95]Kenneth M. Zick, John P. Hayes:
Self-Test and Adaptation for Random Variations in Reliability. FPL 2010: 193-198 - [c94]Kenneth M. Zick, John P. Hayes:
Toward Physically-Adaptive Computing. SASO 2010: 124-133 - [c93]Chien-Chih Yu, John P. Hayes:
Scalable and accurate estimation of probabilistic behavior in sequential circuits. VTS 2010: 165-170
2000 – 2009
- 2009
- [b2]George F. Viamontes, Igor L. Markov, John P. Hayes:
Quantum Circuit Simulation. Springer 2009, ISBN 978-90-481-3064-1, pp. I-X, 1-190 - [j97]Smita Krishnaswamy, Stephen Plaza, Igor L. Markov, John P. Hayes:
Signature-Based SER Analysis and Design of Logic Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(1): 74-86 (2009) - [c92]Smita Krishnaswamy, Igor L. Markov, John P. Hayes:
Improving testability and soft-error resilience through retiming. DAC 2009: 508-513 - [c91]Erik Jan Marinissen, Dae Young Lee, John P. Hayes, Chris Sellathamby, Brian Moore, Steven Slupsky, Laurence Pujol:
Contactless testing: Possibility or pipe-dream? DATE 2009: 676-681 - [c90]Kenneth M. Zick, John P. Hayes:
On-line characterization and reconfiguration for single event upset variations. IOLTS 2009: 243-248 - 2008
- [j96]Ketan N. Patel, Igor L. Markov, John P. Hayes:
Optimal synthesis of linear reversible circuits. Quantum Inf. Comput. 8(3): 282-294 (2008) - [j95]Smita Krishnaswamy, George F. Viamontes, Igor L. Markov, John P. Hayes:
Probabilistic transfer matrices in symbolic reliability analysis of logic circuits. ACM Trans. Design Autom. Electr. Syst. 13(1): 8:1-8:35 (2008) - [c89]Smita Krishnaswamy, Igor L. Markov, John P. Hayes:
On the role of timing masking in reliable logic circuit design. DAC 2008: 924-929 - [c88]Kenneth M. Zick, John P. Hayes:
High-level vulnerability over space and time to insidious soft errors. HLDVT 2008: 161-168 - [c87]Sungsoon Cho, John P. Hayes:
Optimizing router locations for minimum-energy wireless networks. LCN 2008: 544-546 - 2007
- [j94]Smita Krishnaswamy, Igor L. Markov, John P. Hayes:
Tracking Uncertainty with Probabilistic Logic Circuit Testing. IEEE Des. Test Comput. 24(4): 312-321 (2007) - [j93]Jia-Yi Chen, Michael P. Flynn, John P. Hayes:
A Fully Integrated Auto-Calibrated Super-Regenerative Receiver in 0.13-µm CMOS. IEEE J. Solid State Circuits 42(9): 1976-1985 (2007) - [c86]Ramashis Das, John P. Hayes:
Monitoring Transient Errors in Sequential Circuits. ATS 2007: 319-322 - [c85]George F. Viamontes, Igor L. Markov, John P. Hayes:
Checking equivalence of quantum circuits and states. ICCAD 2007: 69-74 - [c84]Smita Krishnaswamy, Stephen Plaza, Igor L. Markov, John P. Hayes:
Enhancing design robustness with reliability-aware resynthesis and logic simulation. ICCAD 2007: 149-154 - [c83]Sungsoon Cho, John P. Hayes:
Power-Aware Link Maintenance (PALM) for Mobile Ad Hoc Networks. LCN 2007: 403-410 - [c82]John P. Hayes, Ilia Polian, Bernd Becker:
An Analysis Framework for Transient-Error Tolerance. VTS 2007: 249-255 - [i1]George F. Viamontes, Igor L. Markov, John P. Hayes:
Checking Equivalence of Quantum Circuits and States. CoRR abs/0705.0017 (2007) - 2006
- [j92]Aditya K. Prasad, Vivek V. Shende, Igor L. Markov, John P. Hayes, Ketan N. Patel:
Data structures and algorithms for simplifying reversible circuits. ACM J. Emerg. Technol. Comput. Syst. 2(4): 277-293 (2006) - [j91]Feng Gao, John P. Hayes:
Gate Sizing and Vt Assignment for Active-Mode Leakage Power Reduction. J. Low Power Electron. 2(2): 230-239 (2006) - [j90]Joonhwan Yi, John P. Hayes:
High-level delay test generation for modular circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(3): 576-590 (2006) - [j89]Feng Gao, John P. Hayes:
Exact and Heuristic Approaches to Input Vector Control for Leakage Power Reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(11): 2564-2571 (2006) - [c81]Ramashis Das, Igor L. Markov, John P. Hayes:
On-Chip Test Generation Using Linear Subspaces. ETS 2006: 111-116 - [c80]Jia-Yi Chen, Michael P. Flynn, John P. Hayes:
A Fully Integrated Auto-Calibrated SuperRegenerative Receiver. ISSCC 2006: 1490-1499 - 2005
- [j88]George F. Viamontes, Igor L. Markov, John P. Hayes:
Is quantum search practical? Comput. Sci. Eng. 7(3): 62-70 (2005) - [j87]Joonhwan Yi, John P. Hayes:
The Coupling Model for Function and Delay Faults. J. Electron. Test. 21(6): 631-649 (2005) - [j86]George F. Viamontes, Igor L. Markov, John P. Hayes:
Graph-based simulation of quantum computation in the density matrix representation. Quantum Inf. Comput. 5(2): 113-130 (2005) - [j85]Nagarajan Kandasamy, John P. Hayes, Brian T. Murray:
Dependable communication synthesis for distributed embedded systems. Reliab. Eng. Syst. Saf. 89(1): 81-92 (2005) - [j84]Amit Chowdhary, John P. Hayes:
Area-optimal technology mapping for field-programmable gate arrays based on lookup tables. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(7): 999-1013 (2005) - [j83]Nagarajan Kandasamy, John P. Hayes, Brian T. Murray:
Time-Constrained Failure Diagnosis in Distributed Embedded Systems: Application to Actuator Diagnosis. IEEE Trans. Parallel Distributed Syst. 16(3): 258-270 (2005) - [c79]John P. Hayes:
Faults and Tests in Quantum Circuits. Asian Test Symposium 2005 - [c78]Ilia Polian, Thomas Fiehn, Bernd Becker, John P. Hayes:
A Family of Logical Fault Models for Reversible Circuits. Asian Test Symposium 2005: 422-427 - [c77]Nagarajan Kandasamy, Sherif Abdelwahed, Gregory C. Sharp, John P. Hayes:
An Online Control Framework for Designing Self-Optimizing Computing Systems: Application to Power Management. Self-star Properties in Complex Information Systems 2005: 174-188 - [c76]Jia-Yi Chen, Michael P. Flynn, John P. Hayes:
A 3.6mW 2.4-GHz multi-channel super-regenerative receiver in 130nm CMOS. CICC 2005: 361-364 - [c75]Feng Gao, John P. Hayes:
Total power reduction in CMOS circuits via gate sizing and multiple threshold voltages. DAC 2005: 31-36 - [c74]Smita Krishnaswamy, George F. Viamontes, Igor L. Markov, John P. Hayes:
Accurate Reliability Evaluation and Enhancement via Probabilistic Transfer Matrices. DATE 2005: 282-287 - [c73]Smita Krishnaswamy, Igor L. Markov, John P. Hayes:
Logic circuit testing for transient faults. ETS 2005: 102-107 - [c72]Ilia Polian, John P. Hayes, Sandip Kundu, Bernd Becker:
Transient fault characterization in dynamic noisy environments. ITC 2005: 10 - [c71]Sungsoon Cho, John P. Hayes:
Impact of mobility on connection in ad hoc networks. WCNC 2005: 1650-1656 - 2004
- [j82]Ketan N. Patel, John P. Hayes, Igor L. Markov:
Fault testing for reversible circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(8): 1220-1230 (2004) - [c70]John P. Hayes, Ilia Polian, Bernd Becker:
Testing for Missing-Gate Faults in Reversible Circuits. Asian Test Symposium 2004: 100-105 - [c69]George F. Viamontes, Igor L. Markov, John P. Hayes:
High-Performance QuIDD-Based Simulation of Quantum Circuits. DATE 2004: 1354-1355 - [c68]Rajesh Venkatasubramanian, John P. Hayes:
Discovering 1-FT Routes in Mobile Ad Hoc Networks. DSN 2004: 627-636 - [c67]Nagarajan Kandasamy, Sherif Abdelwahed, John P. Hayes:
Self-Optimization in Computer Systems via On-Line Control: Application to Power Management. ICAC 2004: 54-61 - [c66]Feng Gao, John P. Hayes:
Exact and heuristic approaches to input vector control for leakage power reduction. ICCAD 2004: 527-532 - [c65]Feng Gao, John P. Hayes:
Gate Sizing and V{t} Assignment for Active-Mode Leakage Power Reduction. ICCD 2004: 258-264 - 2003
- [j81]