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Amit Chowdhary
Person information
- affiliation: Intel Corporation, Santa Clara, CA, USA
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2000 – 2009
- 2006
- [c9]Sherief Reda, Amit Chowdhary:
Effective linear programming based placement methods. ISPD 2006: 186-191 - 2005
- [j5]Amit Chowdhary, John P. Hayes:
Area-optimal technology mapping for field-programmable gate arrays based on lookup tables. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(7): 999-1013 (2005) - [c8]Amit Chowdhary, Karthik Rajagopal, Satish Venkatesan, Tung Cao, Vladimir Tiourin, Yegna Parasuram, Bill Halpin:
How accurately can we model timing in a placement engine? DAC 2005: 801-806 - 2003
- [c7]Sung-Woo Hur, Tung Cao, Karthik Rajagopal, Yegna Parasuram, Amit Chowdhary, Vladimir Tiourin, Bill Halpin:
Force directed mongrel with physical net constraints. DAC 2003: 214-219 - [c6]Karthik Rajagopal, Tal Shaked, Yegna Parasuram, Tung Cao, Amit Chowdhary, Bill Halpin:
Timing driven force directed placement with physical net constraints. ISPD 2003: 60-66 - 2002
- [j4]Amit Chowdhary, Rajesh K. Gupta:
A Methodology for Synthesis of Data Path Circuitse. IEEE Des. Test Comput. 19(6): 90-100 (2002) - [j3]Amit Chowdhary, John P. Hayes:
General technology mapping for field-programmable gate arrays based on lookup tables. ACM Trans. Design Autom. Electr. Syst. 7(1): 1-32 (2002)
1990 – 1999
- 1999
- [j2]Amit Chowdhary, Sudhakar Kale, Phani K. Saripella, Naresh Sehgal, Rajesh K. Gupta:
Extraction of functional regularity in datapath circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(9): 1279-1296 (1999) - 1998
- [c5]Amit Chowdhary, Sudhakar Kale, Phani K. Saripella, Naresh Sehgal, Rajesh K. Gupta:
A general approach for regularity extraction in datapath circuits. ICCAD 1998: 332-339 - 1997
- [b1]Amit Chowdhary:
Technology mapping for field-programmable gate arrays. University of Michigan, USA, 1997 - [c4]Amit Chowdhary, John P. Hayes:
General Modeling and Technology-Mapping Technique for LUT-Based FPGAs. FPGA 1997: 43-49 - 1996
- [j1]Dinesh Bhatia
, Amit Chowdhary:
A Multi-Terminal Net Router for Field-Programmable Gate Arrays. VLSI Design 4(1): 1-10 (1996) - 1995
- [c3]Amit Chowdhary, John P. Hayes:
Technology mapping for field-programmable gate arrays using integer programming. ICCAD 1995: 346-352 - 1994
- [c2]Dinesh Bhatia, Amit Chowdhary, Spyros Tragoudas:
Mathematical model for routability analysis of FPGAs. Great Lakes Symposium on VLSI 1994: 76-79 - [c1]Amit Chowdhary, Dinesh Bhatia:
Detailed Routing of Multi-Terminal Nets in FPGAs. VLSI Design 1994: 237-242
Coauthor Index
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