default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDISLPED 2004: Newport Beach, California, USA
- Rajiv V. Joshi, Kiyoung Choi, Vivek Tiwari, Kaushik Roy:
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004, Newport Beach, California, USA, August 9-11, 2004. ACM 2004
Circuit challenges for scaled technologies
- Ray Bryant:
Why hot chips are no longer "cool". 1 - Michael Liu, Wei-Shen Wang, Michael Orshansky:
Leakage power reduction by dual-vth designs under probabilistic analysis of vth variation. 2-7 - Hari Ananthan, Chris H. Kim, Kaushik Roy:
Larger-than-vdd forward body bias in sub-0.5V nanoscale CMOS. 8-13 - Maurice Meijer, Francesco Pessolano, José Pineda de Gyvez:
Technology exploration for adaptive power and frequency scaling in 90nm CMOS. 14-19 - Suhwan Kim, Stephen V. Kosonocky, Daniel R. Knebel, Kevin Stawiasz:
Experimental measurement of a novel power gating structure with intermediate power saving mode. 20-25
Microarchitecural techniques for power reduction
- Hans M. Jacobson:
Improved clock-gating through transparent pipelining. 26-31 - Zhigang Hu, Alper Buyuktosunoglu, Viji Srinivasan, Victor V. Zyuban, Hans M. Jacobson, Pradip Bose:
Microarchitectural techniques for power gating of execution units. 32-37 - Amirali Baniasadi, Andreas Moshovos:
SEPAS: a highly accurate energy-efficient branch predictor. 38-43 - Yingmin Li, David M. Brooks, Zhigang Hu, Kevin Skadron
, Pradip Bose:
Understanding the energy efficiency of simultaneous multithreading. 44-49
Cache and bus design
- Emil Talpes, Diana Marculescu:
Impact of technology scaling on energy aware execution cache-based microarchitectures. 50-53 - Arindam Mallik, Matthew C. Wildrick, Gokhan Memik:
Design and implementation of correlating caches. 58-61 - Nathaniel Pettis, Le Cai, Yung-Hsiang Lu:
Dynamic power management for streaming data. 62-65 - Maged Ghoneima, Yehea I. Ismail:
Delayed line bus scheme: a low-power bus scheme for coupled on-chip buses. 66-69
System design methodologies
- Deming Chen, Jason Cong:
Delay optimal low-power circuit clustering for FPGAs with dual supply voltages. 70-73 - R. Reed Taylor, Herman Schmit:
Creating a power-aware structured ASIC. 74-77 - Ravindra Jejurikar, Rajesh K. Gupta:
Dynamic voltage scaling for systemwide energy minimization in real-time embedded systems. 78-81 - Hang Su, Peiliang Qiu, Qinru Qiu:
ESACW: an adaptive algorithm for transmission power reduction in wireless networks. 82-85 - Shiva Shankar Ramani, Sanjukta Bhanja:
Any-time probabilistic switching model using bayesian networks. 86-89
Technologies and devices for low-power
- Benton H. Calhoun, Anantha P. Chandrakasan:
Characterizing and modeling minimum energy operation for subthreshold circuits. 90-95 - Bipul Chandra Paul, Arijit Raychowdhury, Kaushik Roy:
Device optimization for ultra-low power digital sub-threshold operation. 96-101 - Keunwoo Kim, Koushik K. Das, Rajiv V. Joshi, Ching-Te Chuang:
Nanoscale CMOS circuit leakage power reduction by double-gate device. 102-107 - Stefanos Kaxiras, Polychronis Xekalakis:
4T-decay sensors: a new class of small, fast, robust, and low-power, temperature/leakage sensors. 108-113
Power optimizations for cache memory
- Chia-Lin Yang, Chien-Hao Lee:
HotSpot cache: joint temporal and spatial locality exploitation for i-cache energy reduction. 114-119 - Rui Min, Wen-Ben Jone, Yiming Hu:
Location cache: a low-power L2 cache system. 120-125 - Chuanjun Zhang, Frank Vahid, Jun Yang, Walid A. Najjar:
A way-halting cache for low-energy high-performance systems. 126-131 - Lin Li, Vijay Degalahal, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin:
Soft error and energy consumption interactions: a data cache perspective. 132-137
Leakage analysis and optimization
- Pietro Babighian, Luca Benini, Alberto Macii, Enrico Macii:
Post-layout leakage power minimization based on distributed sleep transistor insertion. 138-143 - Vishal Khandelwal, Ankur Srivastava:
Active mode leakage reduction using fine-grained forward body biasing strategy. 150-155 - Songqing Zhang, Vineet Wason, Kaustav Banerjee:
A probabilistic framework to estimate full-chips subthreshold leakage power distribution considering within-die and die-to-die P-T-V variations. 156-161 - Dexin Li, Pai H. Chou:
Maximizing efficiency of solar-powered systems by load matching. 162-167
Power supply, voltage, and frequency management
- Chulsung Park, Pai H. Chou:
Power utility maximization for multiple-supply systems by a load-matching switch. 168-173 - Kihwan Choi, Ramakrishna Soma, Massoud Pedram:
Dynamic voltage and frequency scaling based on workload decomposition. 174-179 - Jingcao Hu, Youngsoo Shin, Nagu R. Dhanwada, Radu Marculescu:
Architecting voltage islands in core-based system-on-a-chip designs. 180-185 - John Cornish:
Balanced energy optimization. 186 - Shreekant (Ticky) Thakkar:
Battery life challenges on future mobile notebook platforms. 187
Power-efficient bus design
- Rahul M. Rao, Kanak Agarwal, Dennis Sylvester, Richard B. Brown, Kevin J. Nowka, Sani R. Nassif:
Approaches to run-time and standby mode leakage reduction in global buses. 188-193 - Himanshu Kaul, Dennis Sylvester, Mark A. Anders, Ram Krishnamurthy:
Spatial encoding circuit techniques for peak power reduction of on-chip high-performance buses. 194-199 - Sarvesh H. Kulkarni, Ashish Srivastava, Dennis Sylvester:
A new algorithm for improved VDD assignment in low power dual VDD systems. 200-205 - Sabino Salerno, Alberto Bocca, Enrico Macii, Massimo Poncino:
Limited intra-word transition codes: an energy-efficient bus encoding for LCD display interfaces. 206-211
High level power modeling and analysis
- Nam Sung Kim, Taeho Kgil, Valeria Bertacco, Todd M. Austin, Trevor N. Mudge:
Microarchitectural power modeling techniques for deep sub-micron microprocessors. 212-217 - Seongmoo Heo, Krste Asanovic:
Power-optimal pipelining in deep submicron technology. 218-223 - Chandra Krintz, Ye Wen, Richard Wolski:
Application-level prediction of battery dissipation. 224-229 - Alireza Mehrnia, Babak Daneshrad:
Minimizing power consumption and complexity in a programmable transmit filter bank for OFDM. 230-235
Circuit technologies
- Baohua Wang, Pinaki Mazumder:
On optimality of adiabatic switching in MOS energy-recovery circuit. 236-239 - Joohee Kim, Marios C. Papaefthymiou:
Constant-load energy recovery memory for efficient high-speed operation. 240-243 - Jing-Hong Conan Zhan, Jon S. Duster, Kevin T. Kornegay:
A comparative study of MOS VCOs for low voltage high performance operation. 244-247 - Bhaskar Chatterjee, Manoj Sachdev, Ram Krishnamurthy:
A CPL-based dual supply 32-bit ALU for sub 180nm CMOS technologies. 248-251
Low power converter circuits
- Hui-Chin Tseng, Hsin-Hung Ou, Chi-Sheng Lin, Bin-Da Liu:
A low-power rail-to-rail 6-bit flash ADC based on a novel complementary average-value approach. 252-256 - Chuang Zhang, Dongsheng Ma, Ashok Kumar Srivastava:
Integrated adaptive DC/DC conversion with adaptive pulse-train technique for low-ripple fast-response regulation. 257-262 - Gerhard Schrom, Peter Hazucha, Jae-Hong Hahn, Volkan Kursun, Donald S. Gardner, Siva G. Narendra, Tanay Karnik, Vivek De:
Feasibility of monolithic and 3D-stacked DC-DC converters for microprocessors in 90nm technology generation. 263-268 - Stefano Gregori, Yunlei Li, Huijuan Li, Jin Liu, Franco Maloberti:
2.45 GHz power and data transmission for a low-power autonomous sensors platform. 269-273 - Lawrence T. Clark, Rakesh Patel, Timothy S. Beatty:
Managing standby and active mode leakage power in deep sub-micron design. 274-279
Circuits for low power wireless
- Marian Verhelst, Wim Vereecken, Michiel Steyaert, Wim Dehaene:
Architectures for low power ultra-wideband radio receivers in the 3.1-5GHz band for data rates < 10Mbps. 280-285 - Mohamed Kawokgy, C. André T. Salama:
Low-power asynchronous viterbi decoder for wireless applications. 286-289 - Ming-Feng Huang, Shuenn-Yuh Lee, Chung J. Kuo:
A CMOS even harmonic mixer with current reuse for low power applications. 290-295 - M. Ali-Bakhshian, K. Sadeghi:
A novel continuous-time common-mode feedback for low-voltage switched-OPAMP. 296-300
Power efficient design for arithmetic circuits
- Yijun Liu, Stephen B. Furber:
The design of a low power asynchronous multiplier. 301-306 - Jinn-Shyan Wang, Chien-Nan Kuo, Tsung-Han Yang:
Low-power fixed-width array multipliers. 307-312 - Hiroaki Suzuki, Woopyo Jeong, Kaushik Roy:
Low-power carry-select adder using adaptive supply voltage based on input vector patterns. 313-318 - Seokwoo Lee, Shidhartha Das, Toan Pham, Todd M. Austin, David T. Blaauw, Trevor N. Mudge:
Reducing pipeline energy demands with local DVS and dynamic retiming. 319-324 - Supriyo Datta:
Understanding nanoscale conductors. 325
Energy efficient architectural techniques
- Kim M. Hazelwood, David M. Brooks:
Eliminating voltage emergencies via microarchitectural voltage control feedback and dynamic optimization. 326-331 - Baohua Wang, Pinaki Mazumder:
On optimality of adiabatic switching in MOS energy-recovery circuit. 332-337 - Chanik Park, Jeong-Uk Kang, Seon-Yeong Park, Jinsoo Kim:
Energy-aware demand paging on NAND flash-based embedded storages. 338-343 - Diana Marculescu:
Application adaptive energy efficient clustered architectures. 344-349 - Sani R. Nassif:
The impact of variability on power. 350
Wireless application drivers for low-power systems
- Bo-Cheng Lai, David Hwang, Sungha Pete Kim, Ingrid Verbauwhede:
Reducing radio energy consumption of key management protocols for wireless sensor networks. 351-356 - Feng Zhou, Chunhong Chen, Dawei Jin, Chenling Huang, Hao Min:
Evaluating and optimizing power consumption of anti-collision protocols for applications in RFID systems. 357-362 - Vijay Raghunathan, Trevor Pering, Roy Want, Alex Nguyen, Peter Jensen:
Experience with a low power wireless mobile computing platform. 363-368 - Luca Negri, Mariagiovanna Sami, David Macii, Alessandra Terranegra:
FSM--based power modeling of wireless protocols: the case of bluetooth. 369-374
Adaptive voltage scaling
- Mohamed Elgebaly, Manoj Sachdev:
Efficient adaptive voltage scaling system through on-chip critical path emulation. 375-380 - Bita Gorjiara, Nader Bagherzadeh, Pai H. Chou:
An efficient voltage scaling algorithm for complex SoCs with few number of voltage modes. 381-386 - Youngjin Cho, Naehyuck Chang:
Memory-aware energy-optimal frequency assignment for dynamic supply voltage scaling. 387-392 - Woonseok Kim, Jihong Kim, Sang Lyul Min:
Preemption-aware dynamic voltage scaling in hard real-time systems. 393-398
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-11-27 01:10 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
