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ORCID34th ISMVL 2004: Toronto, Canada
- 34th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2004), 19-22 May 2004, Toronto, Canada. IEEE Computer Society 2004, ISBN 0-7695-2130-4
Keynote Address
- Jonathan Rose:
Hard vs. Soft: The Central Question of Pre-Fabricated Silicon. 2-5
Emerging Technologies
- Yuki Tsuji, Takao Waho:
Multiple-Input Resonant-Tunneling Logic Gates for Flash A/D Converter Applications. 8-13 - Arijit Raychowdhury, Kaushik Roy:
A Novel Multiple-Valued Logic Design Using Ballistic Carbon Nanotube FETs. 14-19 - Tomohiro Takahashi, Takahiro Hanyu:
Multiple-Valued Multiple-Rail Encoding Scheme for Low-Power Asynchronous Communication. 20-25 - Haque Mohammad Munirul, Michitaka Kameyama:
Ultra-Fine-Grain Field-Programmable VLSI Using Multiple-Valued Source-Coupled Logic. 26-30
Logic
- Viorica Sofronie-Stokkermans:
Resolution-Based Decision Procedures for the Positive Theory of Some Finitely Generated Varieties of Algebras. 32-37 - Stefano Aguzzoli:
Uniform Description of Calculi for All t-Norm Logics. 38-43 - Mayuka F. Kawaguchi, Masaaki Miyakoshi:
Weakly Associative Functions on [0, 1] as Logical Connectives. 44-48 - Brunella Gerla:
Automata over MV-Algebra. 49-54
Invited Address
- Gilles Brassard:
Quantum Communication Complexity: A Survey. 56
Reversible Logic
- Mozammel H. A. Khan, Marek A. Perkowski, Mujibur R. Khan:
Ternary Galois Field Expansions for Reversible Logic and Kronecker Decision Diagrams for Ternary GFSOP Minimization. 58-67 - Pawel Kerntopf, Marek A. Perkowski, Mozammel H. A. Khan:
On Universality of General Reversible Multiple-Valued Logic Gates. 68-73 - D. Michael Miller, Gerhard W. Dueck, Dmitri Maslov:
A Synthesis Method for MVL Reversible Logi. 74-80 - Anas N. Al-Rabadi:
Reversible Fast Permutation Transforms for Quantum Circuit Synthesi. 81-86 - Anas Al-Rabadi:
Quantum Circuit Synthesis Using Classes of GF(3) Reversible Fast Spectral Transforms. 87-93
Clones
- Lucien Haddad, Dietlinde Lau:
On Partial Clones containing Maximal Clones. 96-101 - Hajime Machida, Ivo G. Rosenberg:
Monoids whose Centralizer is the Least Clone. 102-108 - Grant Pogosyan, Ivo G. Rosenberg:
Algebraic Properties of Totally Irreducible Elements of Clone Lattices. 109-114 - Jovanka Pantovic
, Gradimir Vojvodic:
Minimal Partial Hyperclones on a Two-Element Set. 115-119 - Boris A. Romov:
Some Properties of Local Partial Clones on an Infinite Set. 120-125
Circuits I
- Hideki Fukuda:
Signed Digit CMOS (SD-CMOS) Logic Circuits with Static Operation. 128-134 - Omid Mirmotahari, Yngvar Berg:
A Systolic Parallel Multiplier over GF(3m) Using Neuron-MOS DLC. 135-138
Fuzzy Logic and Learning
- Dan Mihai:
Optimizing the Defuzzifier Timing for the Fuzzy Control of a Servodrive. 142-147 - Claudio Moraga:
A Metasemantics to Refine Fuzzy If-Then Rules. 148-153 - Alioune Ngom, Dan A. Simovici, Ivan Stojmenovic:
Evolutionary Strategy for Learning Multiple-Valued Logic Functions. 154-160
Reed Muller Expansions
- Bogdan J. Falkowski, Cicilia C. Lozano, Susanto Rahardja:
Fast Optimization of Fixed-Polarity Reed-Muller Expansions over GF(5). 162-167 - K. J. Adams, J. McGregor:
On the Optimisation of Reed-Muller Expressions. 168-176 - Bogdan J. Falkowski, Cicilia C. Lozano, Susanto Rahardja:
Spectra Generation for Fixed-Polarity Reed-Muller Transform over GF(5). 177-183 - Radomir S. Stankovic, Claudio Moraga, Jaakko Astola:
Derivatives for Multiple-Valued Functions Induced by Galois Field and Reed-Muller-Fourier Expressions. 184-189
Circuits II
- Akira Mochizuki, Takashi Takeuchi, Takahiro Hanyu:
Intra-Chip Address-Presetting Data-Transfer Scheme Using Four-Valued Encoding. 192-197 - Soo Jin Park, Byoung Hee Yoon, Kwang Sub Yoon, Heung Soo Kim:
Design of Quaternary Logic Gate Using Double Pass-Transistor Logic with Neuron MOS Down Literal Circuit. 198-203 - Daniel H.-Y. Teng, Ronald J. Bolton:
A Self-Restored Current-Mode CMOS Multiple-Valued Logic Design Technique and its Applications. 204-209 - Omid Mirmotahari, Yngvar Berg:
A Novel D-Latch in Multiple-Valued Semi-Floating-Gate Recharged Logic. 210-213
MDDs
- Shinobu Nagayama, Tsutomu Sasao:
On the Minimization of Average Path Lengths for Heterogeneous MDDs. 216-222 - Dragan Jankovic, Radomir S. Stankovic, Rolf Drechsler:
Reduction of Sizes of Multi-Valued Decision Diagrams by Copy Propertie. 223-228 - Radomir S. Stankovic, Jaakko Astola:
Edge-Valued Decision Diagrams for Multiple-Valued Functions. 229-234 - Görschwin Fey, Rolf Drechsler, Maciej J. Ciesielski:
Algorithms for Taylor Expansion Diagrams. 235-240
Mathematical Aspects
- Dietmar Schweigert:
Polynomial Functions on a Central Relation. 242-244 - Sergiu Rudeanu, Dan A. Simovici:
A Graph-Theoretical Approach to Boolean Interpolation of Non-Boolean Functions. 245-250 - Carlos Ansótegui, Ramón Béjar, Alba Cabiscol, Felip Manyà:
The Interface between P and NP in Signed CNF Formulas. 251-256 - Michiro Kondo:
Characterization Theorem of Lattice Implication Algebra. 257-260
Single Electron Logic
- Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi, Hiroshi Inokawa, Yasuo Takahashi:
A Single-Electron-Transistor Logic Gate Family and Its Application - Part I: Basic Components for Binary, Multiple-Valued and Mixed-Mode Logic. 262-268 - Hiroshi Inokawa, Yasuo Takahashi, Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi:
A Single-Electron-Transistor Logic Gate Family and Its Application - Part II: Design and Simulation of a 7-3 Parallel Counter with Linear Summation and Multiple-Valued Latch Functions. 269-274 - Svetlana N. Yanushkevich, Vlad P. Shmerko, L. Guy, D. C. Lu:
Three Dimensional Multiple Valued Circuits Design Based on Single-Electron Logic. 275-280
Probability & Uncertainty
- Arnon Avron, Iddo Lev:
Non-Deterministic Matrices. 282-287 - Denis V. Popel, Elena I. Popel:
Controlling Uncertainty in Discretization of Continuous Data. 288-293 - Charles G. Morgan:
Many Valued Probability Theory. 294-299
Digital Design
- Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura:
A Method to Evaluate Logic Functions in the Presence of Unknown Inputs Using LUT Cascades. 302-308 - Elena Dubrova:
A Polynomial Time Algorithm for Non-Disjoint Decomposition of Multiple-Valued Functions. 309-314 - Mostafa I. H. Abd-El-Barr, Louai Al-Awami:
Iterative-Based Minimization of Unary 4-Valued Functions for Current-Mode CMOS Realization. 315-320 - Hafiz Md. Hasan Babu, Moinul Islam Zaber, Md. Rafiqul Islam, Md. Mazder Rahman:
On the Minimization of Multiple-Valued Input Binary-Valued Output Functions. 321-326
Circuits III
- Haque Mohammad Munirul, Michitaka Kameyama:
Multiple-Valued Source-Coupled Logic VLSI Based on Adaptive Threshold Control and Its Applications. 328-333 - Kazuya Ishida, Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi:
Design and Verification of Parallel Multipliers Using Arithmetic Description Language: ARITH. 334-339 - Hiromitsu Kimura, Kostas Pagiamtzis, Ali Sheikholeslami, Takahiro Hanyu:
A Study of Multiple-Valued Magnetoresistive RAM (MRAM) Using Binary MTJ Devices. 340-345 - Yngvar Berg, Snorre Aunet, Øivind Næss, Omid Mirmotahari:
Basic Multiple-Valued Functions Using Recharge CMOS Logic. 346-351
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