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ORCIDSoC 2003, Tampere, Finland
- Proceedings of the 2003 International Symposium on System-on-Chip, Tampere, Finland, November 19-21, 2003. IEEE 2003, ISBN 0-7803-8160-2
- Bernardo Kastrup, Antoine van Wel:
Moustique: smaller than an ASIC and fully programmable. - Andreas Hoffmann, Richard Langridge, Dave Machin:
SoC integration of programmable cores. - Hans-Martin Blüthgen, Cyprian Grassmann, Wolfgang Raab, Ulrich Ramacher:
A programmable platform for software-defined radio. - Salvatore Talluto:
CTL based DFT solution to accelerate design to test development for system on chip devices. - Chris Rowen, Steve Leibson:
SOC logic development using configurable, application-specific processors. - Brian Dalay:
Accelerating system performance using SOPC builder. 3-5 - Sunghyun Jee, Kannappan Palaniappan:
Performance of dynamically scheduling VLIW instructions. 7-10 - Juha Kylliäinen, Jari Nurmi, Mika Kuulusa:
COFFEE - a core for free. 17-22 - Dirk Killat, Joachim Schmidt, Andreas Baumgaertner, Robert Baraniecki, Oliver Salzmann:
One-chip solution in 0.35 μm standard CMOS for electronic ballasts for fluorescent lamps. 23-26 - Tommi Salminen, Juha-Pekka Soininen:
Evaluating application mapping using network simulation. 27-30 - Jian Liu, Li-Rong Zheng, Hannu Tenhunen:
A guaranteed-throughput switch for network-on-chip. 31-34 - E. G. Nikolova, David J. Mulvaney, Vassilios A. Chouliaras, José L. Núñez-Yáñez:
A code compression scheme for improving SoC performance. 35-40 - Youngwoo Kim, Kyoung Park, Myungjoon Kim:
AMBA based multiprocessor system. 41-42 - Mikko Ylinen, Adrian Burian, Jarmo Takala:
Updating matrix inverse in fixed-point representation: direct versus iterative methods. 45-48 - Hany Ghattas, M. Mbaye, J. Pepga Bissou, Yvon Savaria:
SoC platform architecture for a network processor. 49-52 - Tony Kirkham, Tughrul Arslan, Fred Westall, David H. Crawford:
A low power datapath for algebraic codebook search targeting a generic GSM system-on-chip platform. 53-56 - Olli Lehtoranta, Timo D. Hämäläinen:
Complexity analysis of spatially scalable MPEG-4 encoder. 57-60 - Tapio Ristimäki, Jari Nurmi
:
Implementing user and application specific algorithms within IP-methodology: a coarse-grain-approach. 61-64 - Jari Heikkinen, Tommi Rantanen, Andrea G. M. Cilio, Jarmo Takala, Henk Corporaal:
Immediate optimization for compressed transport triggered architecture instructions. 65-68 - Claudio Mucci, Carlo Chiesa, Andrea Lodi, Mario Toma, Fabio Campi:
A C-based algorithm development flow for a reconfigurable processor architecture. 69-73 - Christian Panis, J. Hohl, Herbert Grünbacher, Jari Nurmi:
xICU - in interrupt control unit for a configurable DSP core. 75-78 - T. Andrei Bartic, Jean-Yves Mignolet, Vincent Nollet, Théodore Marescaux, Diederik Verkest, Serge Vernalde, Rudy Lauwereins:
Highly scalable network on chip for reconfigurable systems. 79-82 - Manoj Ariyamparambath, Denis Bussaglia, Bernd Reinkemeier, Tim Kogel, Torsten Kempf:
A highly efficient modeling style for heterogeneous bus architectures. 83-87 - Tiberiu Seceleanu, Juha Plosila:
Modeling on-chip communication. 89-92 - Ilhan Hatirnaz, Yusuf Leblebici:
Twisted differential on-chip interconnect architecture for inductive/capacitive crosstalk noise cancellation. 93-96 - Kanak Agarwal, Dennis Sylvester, David T. Blaauw:
Dynamic clamping: on-chip dynamic shielding and termination for high-speed RLC buses. 97-100 - Markus Tahedl, Hans-Jörg Pfleiderer:
A driver load model for capacitive coupled on-chip interconnect buses. 101-104 - Tero Kangas, Jouni Riihimäki, Erno Salminen, Kimmo Kuusilinna, Timo D. Hämäläinen:
Using a communication generator in SoC architecture exploration. 105-108 - Kim Rounioja, Jari A. Parviainen:
Arithmetic processing unit for reciprocal operations. 109-112 - Heikki Kariniemi, Jari Nurmi:
New adaptive routing algorithm for extended generalized fat trees on-chip. 113-118 - Jari Kreku, Juha-Pekka Soininen:
Mappability estimate: a measure of the goodness of a processor-algorithm pair. 119-122 - Andrei Mekler, Jaan Raik:
Multiple-objective backtrace for solving test generation constraints. 123-126 - Massimo Bocchi, Claudio Brunelli, Claudia De Bartolomeis, Luca Magagni, Fabio Campi:
A system level IP integration methodology for fast SOC design. 127-130 - Ulrich Hirnschrott, Andreas Krall:
VLIW operation refinement for reducing energy consumption. 131-134 - Mohd. Hasan, Tughrul Arslan, John S. Thompson:
A delay spread based low power reconfigurable FFT processor architecture for wireless receiver. 135-138 - José Antonio Moreno Zamora, Pedro José Rodriguez Corrales, Juan Manuel Sánchez-Pérez:
Design of a parametrizable low cost Ethernet MAC core for SoC solutions. 139-142 - Jerzy J. Dabrowski:
Lookback BiST for RF front-ends in digital transceivers. 143-146 - Jan Madsen, Kashif Virk, Mercury Gonzales:
Abstract RTOS modeling for multiprocessor system-on-chip. 147-150 - Robert Bai, Dennis Sylvester:
Analysis and design of level-converting flip-flops for dual-Vdd/Vth integrated circuits. 151-154 - Jaeseo Lee, Geoff Hatcher, Lieven Vandenberghe, Chih-Kong Ken Yang:
Evaluation of fully-integrated switching regulators for CMOS process technologies. 155-158 - Eduardo Braulio Wanderley Netto, Rodolfo Azevedo, Paulo Centoducatte, Guido Araujo:
Mixed static/dynamic profiling for dictionary based code compression. 159-163 - Jeroen A. J. Leijten, Geoffrey Burns, Jos Huisken, Erwin Waterlander, Antoine van Wel:
AVISPA: a massively parallel reconfigurable accelerator. 165-168
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