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ORCIDITC-Asia 2023: Matsue, Japan
- IEEE International Test Conference in Asia, ITC-Asia 2023, Matsue, Japan, September 12-14, 2023. IEEE 2023, ISBN 979-8-3503-1281-2
- Hao-Chiao Hong
, Chien-Hung Chen, Yu-Wun Chen:
Parametric Faults in Computing-in-Memory Applications of a 4kb Read-Decoupled 8T SRAM Array in 40nm CMOS. 1-5 - Shogo Tokai, Daichi Akamatsu, Hiroyuki Yotsuyanagi, Masaki Hashizume:
On Test Pattern Generation Method for an Approximate Multiplier Considering Acceptable Faults. 1-6 - Yuki Yamanaka, Masayuki Arai, Yoshikazu Nagamura, Satoshi Fukumoto:
Toward Improvement and Evaluation of Reconstruction Capability of CapsNet-Based Wafer Map Defect Pattern Classifier. 1-6 - Liang Hong, Ge Zhu, Jing Zhou, Xuefei Li, Ziyi Chen, Wei Hu:
Hunting for Hardware Trojan in Gate Netlist: A Stacking Ensemble Learning Perspective. 1-6 - Janet Olson:
Test industry challenges and solutions as observed by the leading physical implementation solution provider : Invited Talk 2. 1 - Shyue-Kung Lu, Xin Dong:
Integrated Progressive Built-In Self-Repair (IPBISR) Techniques for NAND Flash Memory. 1-6 - Mohd Amiruddin Zainol, Sompon Khamron, Ng Gua Bin:
Optimizing Post-Silicon Validation for FPGA Serial Configuration using an Automation Framework and Timing Characterization Verification. 1-6 - Aibin Yan, Fan Xia, Tianming Ni, Jie Cui, Zhengfeng Huang, Patrick Girard, Xiaoqing Wen:
A Low Overhead and Double-Node-Upset Self-Recoverable Latch. 1-5 - Hao Cheng, Chi-Jhe Li, Hung-Lin Chen, Jiun-Lang Huang:
BDD-Based Self-Test Program Generation for Processor Cores. 1-6 - Xuejian Li, Zhengguang Zhu:
Software Defect Detection Based on Feature Fusion and Alias Analysis. 1-6 - Po-Yao Chuang, Francesco Lorenzelli, Erik Jan Marinissen:
Generating Test Patterns for Chiplet Interconnects: Achieving Optimal Effectiveness and Efficiency. 1-6 - Aibin Yan, Jing Xiang, Zhengfeng Huang, Tianming Ni, Jie Cui, Patrick Girard, Xiaoqing Wen:
Design of A Highly Reliable and Low-Power SRAM With Double-Node Upset Recovery for Safety-critical Applications. 1-6 - Shintaro Yamamichi:
Technology for The Future of Computing : Keynote 2. 1 - Wei-Ji Chao, Tong-Yu Hsieh:
Cost-Effective Error-Mitigation for High Memory Error Rate of DNN: A Case Study on YOLOv4. 1-6 - Meng-Shan Wu, Yen-Lin Chua, Jin-Fu Li, Yun-Ting Chuan, Shih-Hsu Huang:
Fault-Aware ECC Scheme for Enhancing the Read Reliability of STT-MRAMs. 1-6 - Bin Zhang, Ye Cai, Zhiheng He, Sen Liang, Wei He:
Structured DFT Development Approach for Chisel-Based High Performance RISC-V Processors. 1-6 - Anwesh Kumar Samal, Sandeep Kumar, Atin Mukherjee:
Design of Single Node Upset Resilient Latch for Low Power, Low Cost and Highly Robust Applications. 1-5 - Yi-Hsuan Lee, Wei-Hao Chen, Shi-Yu Huang:
Self-Sufficient Clock Jitter Measurement Methodology Using Dithering-Based Calibration. 1-6 - Lee Harrison, Wu Yang:
Scalable hierarchical DFT technologies for AI, SOC and multi-die : Tutorial 1. 1 - Yasumitsu Orii:
Semiconductor Packaging Revolution in the Era of Chiplets : Keynote 1. 1 - Kentaroh Katoh, Shuhei Yamamoto, Zheming Zhao, Yujie Zhao, Shogo Katayama, Anna Kuwana, Takayuki Nakatani, Kazumi Hatayama, Haruo Kobayashi, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa:
A Physically Unclonable Function Using Time-to-Digital Converter with Linearity Self-Calibration and its FPGA Implementation. 1-6 - Ayano Takaya, Michihiro Shintani:
Feasibility Study of Incremental Neural Network Based Test Escape Detection by Introducing Transfer Learning Technique. 1-6 - Erik Jan Marinissen:
Moore Meets Murphy : Invited Talk 1. 1 - David C. Keezer, Dany Minier, Hongjie Li:
Experimental Evaluation of Jitter Reduction Methods for Multi-Gigahertz Test. 1-6 - Yervant Zorian:
Silicon Lifecycle Management: Trends, Challenges and Solutions : Tutorial 2. 1 - Aibin Yan, Chao Zhou, Shaojie Wei, Jie Cui, Zhengfeng Huang, Patrick Girard, Xiaoqing Wen:
Design of a Novel Latch with Quadruple-Node-Upset Recovery for Harsh Radiation Hardness. 1-6 - Chen-Lin Tsai, Shi-Yu Huang:
Trustworthy Lifetime Prediction by Aging History Analysis and Multi-Level Stress Test. 1-6
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