default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID13th MEMOCODE 2015: Austin, TX, USA
- 13. ACM/IEEE International Conference on Formal Methods and Models for Codesign, MEMOCODE 2015, Austin, TX, USA, September 21-23, 2015. IEEE 2015, ISBN 978-1-5090-0237-5
- Rajeev Alur:
Keynote talk I: Syntax-guided synthesis. 1 - Alon Brook, Doron A. Peled, Sven Schewe
:
Local and global fairness in concurrent systems. 2-9 - Karsten Rathlev, Steven Smyth, Christian Motika, Reinhard von Hanxleden, Michael Mendler:
SCEst: Sequentially constructive esterel. 10-19 - Wenchao Li, Léonard Gérard, Natarajan Shankar:
Design and verification of multi-rate distributed systems. 20-29 - Ahlem Triki, Jacques Combaz, Saddek Bensalem:
Optimized distributed implementation of timed component-based systems. 30-35 - Jean-Pierre Talpin, Pierre Jouvelot, Sandeep Kumar Shukla:
Towards refinement types for time-dependent data-flow networks. 36-41 - Alan Leung, Dimitar Bounov, Sorin Lerner:
C-to-Verilog translation validation. 42-47 - Peter A. Milder:
MEMOCODE 2015 design contest: Continuous skyline computation. 48-51 - Kenichi Koizumi, Mary Inaba, Kei Hiraki:
Efficient implementation of continuous skyline computation on a multi-core processor. 52-55 - Ehsan Montahaie, Milad Ghafouri, Saied Rahmani, Hanie Ghasemi, Farzad Sharif Bakhtiar, Rashid Zamanshoar, Kianoush Jafari, Mohsen Gavahi, Reza Mirzaei, Armin Ahmadzadeh, Saeid Gorgin:
Efficient continuous skyline computation on multi-core processors based on Manhattan distance. 56-59 - Derek Chiou:
Keynote talk II: Accelerating data centers using reconfigurable logic. 60 - Abdur Rakib, Hafiz Mahfooz Ul Haque:
Modeling and verifying context-aware non-monotonic reasoning agents. 61-69 - Adel Dokhanchi, Bardh Hoxha, Georgios Fainekos:
Metric interval temporal logic specification elicitation and debugging. 70-79 - Paolo Arcaini, Silvia Bonfanti, Angelo Gargantini, Atif Mashkoor, Elvinia Riccobene:
Formal validation and verification of a medical software critical component. 80-89 - Michael W. Whalen, Sanjai Rayadurgam, Elaheh Ghassabani, Anitha Murugesan, Oleg Sokolsky, Mats Per Erik Heimdahl, Insup Lee:
Hierarchical multi-formalism proofs of cyber-physical systems. 90-95 - João Bastos, Sander Stuijk, Jeroen Voeten, Ramon R. H. Schiffelers, Johan Jacobs, Henk Corporaal:
Modeling resource sharing using FSM-SADF. 96-101 - Masahiro Fujita:
Logic analysis and optimization with quick identification of invariants through one time frame analysis. 102-107 - David J. Greaves:
Layering RTL, SAFL, Handel-C and Bluespec constructs on Chisel HCL. 108-117 - Jonathan Beaumont, Andrey Mokhov, Danil Sokolov, Alex Yakovlev:
Compositional design of asynchronous circuits from behavioural concepts. 118-127 - Matthew Naylor, Simon W. Moore:
A generic synthesisable test bench. 128-137 - William Durand, Sébastien Salva:
Passive testing of production systems based on model inference. 138-147 - Paul C. Attie, Ali Cherri, Kinan Dak-Al-Bab, Mouhammad Sakr, Jad Saklawi:
Model and program repair via SAT solving. 148-157 - Stefan Kugele, Gheorghe Pucea, Ramona Popa, Laurent Dieudonné, Horst Eckardt:
On the deployment problem of embedded systems. 158-167 - Paul Clements:
Keynote Talk III: A formal methods perspective on product line engineering. 168 - Jan Láník, Julien Legriel, Erwan Piriou, Emmanuel Viaud, Fahim Rahim, Oded Maler, Solaiman Rahim:
Reducing power with activity trigger analysis. 169-178 - Bingyi Cao, Kenneth A. Ross, Martha A. Kim, Stephen A. Edwards:
Implementing latency-insensitive dataflow blocks. 179-187 - Alexandru Tanase, Michael Witterauf, Jürgen Teich, Frank Hannig:
Symbolic loop parallelization for balancing I/O and memory accesses on processor arrays. 188-197 - Sanne Wouda, Sebastiaan J. C. Joosten, Julien Schmaltz:
Process algebra semantics & reachability analysis for micro-architectural models of communication fabrics. 198-207 - Martial Chabot, Kévin Mazet, Laurence Pierre:
Automatic and configurable instrumentation of C programs with temporal assertion checkers. 208-217 - Stefan Jaksic, Ezio Bartocci, Radu Grosu, Reinhard Kloibhofer, Thang Nguyen, Dejan Nickovic:
From signal temporal logic to FPGA monitors. 218-227 - Pierre Ganty, Samir Genaim, Ratan Lal, Pavithra Prabhakar:
From non-zenoness verification to termination. 228-237 - Xian Li, Klaus Schneider:
Verification condition generation for hybrid systems. 238-247 - Daniel Ricketts, Gregory Malecha, Mario M. Alvarez, Vignesh Gowda, Sorin Lerner:
Towards verification of hybrid systems in a foundational proof assistant. 248-257
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-01-23 20:17 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
