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ORCIDMasahiro Fujita
This is just a disambiguation page, and is not intended to be the bibliography of an actual person. Any publication listed on this page has not been assigned to an actual author yet. If you know the true author of one of the publications listed below, you are welcome to contact us.
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2020 – today
- 2024
[j127]Heming Sun
, Qingyang Yi, Masahiro Fujita:
FPGA Codec System of Learned Image Compression With Algorithm-Architecture Co-Optimization. IEEE J. Emerg. Sel. Topics Circuits Syst. 14(2): 334-347 (2024)- [j126]Masahiro Fujita, Yasunori Kawanami, Kiyokazu Miyazawa, Masaya Kinoshita, Kunihito Sawai, Fuminori Yamasaki, Tatsuya Matsui, Ken Endo, Shu Ishiguro, Hiroaki Kitano:
Stories of QRIO and PINO, and Beyond: Lessons Learned from Small Humanoid Projects From R&D to Business. Int. J. Humanoid Robotics 21(1) (2024) - [j125]J. Sharailin Gidon, Jintu Borah, Smrutirekha Sahoo, Shubhankar Majumdar, Masahiro Fujita:
Bidirectional LSTM Model for Accurate and Real-Time Landslide Detection: A Case Study in Mawiongrim, Meghalaya, India. IEEE Internet Things J. 11(3): 3792-3800 (2024) - [c358]Sai Sanjeet, Sanchari Das, Shiuh-Hua Wood Chiang, Masahiro Fujita, Bibhu Datta Sahoo:
Systematic Design of Ring VCO-Based SNN - Translating Training Parameters to Circuits -. MWSCAS 2024: 1212-1216 - [c357]Yusuke Kimura, Shaowen Li, Hiroyuki Sato, Masahiro Fujita:
Accelerating Decision Diagram-based Multi-node Quantum Simulation with Ring Communication and Automatic SWAP Insertion. QSW 2024: 107-115 - [i7]Yusuke Kimura, Shaowen Li, Hiroyuki Sato, Masahiro Fujita:
Accelerating Decision Diagram-based Multi-node Quantum Simulation with Ring Communication and Automatic SWAP Insertion. CoRR abs/2405.09033 (2024) - 2023
- [j124]Jitendra Kumar, Yukio Miyasaka, Asutosh Srivastava, Masahiro Fujita:
Formal Verification of Integer Multiplier Circuits Using Binary Decision Diagrams. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(4): 1365-1378 (2023) - [j123]Sai Sanjeet, Bibhu Datta Sahoo, Masahiro Fujita:
Energy-Efficient FPGA Implementation of Power-of-2 Weights-Based Convolutional Neural Networks With Low Bit-Precision Input Images. IEEE Trans. Circuits Syst. II Express Briefs 70(2): 741-745 (2023) - [c356]Sai Sanjeet, Sannidhi Boppana, Bibhu Datta Sahoo, Masahiro Fujita:
Noise Resilience of Reduced Precision Neural Networks. HEART 2023: 114-118 - [c355]Ahmed Kiyoshi Sugihara, Takehisa Wada, Tamotsu Suda, Masahiro Fujita, Shigeo Kawasaki, Osamu Mori:
Wireless Reference Frequency Distribution for Membrane-Deployed Distributed Microwave Interferometer Concept. IGARSS 2023: 4266-4269 - [c354]Sai Sanjeet, Rahul K. Meena, Bibhu Datta Sahoo, Keshab K. Parhi, Masahiro Fujita:
IIR Filter-Based Spiking Neural Network. ISCAS 2023: 1-5 - [c353]Pooja Choudhary, Lava Bhargava, G. U. Vinod, Ashok Kumar Suhag, Masahiro Fujita, Virendra Singh:
Optimization of Imprecise Multiplier Circuits by using Binary Decision Diagram. iSES 2023: 115-120 - [c352]Pooja Choudhary, Lava Bhargava, Masahiro Fujita, Virendra Singh:
LUT-based Arithmetic Circuit Approximation with Formal Guarantee on Worst Case Relative Error. LATS 2023: 1-2 - [c351]Shaowen Li, Yusuke Kimura, Hiroyuki Sato, Junwei Yu, Masahiro Fujita:
Parallelizing quantum simulation with decision diagrams. QSW 2023: 149-154 - [i6]Shaowen Li, Yusuke Kimura, Hiroyuki Sato, Junwei Yu, Masahiro Fujita:
Parallelizing quantum simulation with decision diagrams. CoRR abs/2312.01570 (2023) - 2022
- [j122]Pooja Choudhary, Lava Bhargava, Masahiro Fujita, Virendra Singh, Ashok Kumar Suhag:
Approximating Arithmetic Circuits for IoT Devices Data Processing. Comput. Ind. Eng. 174: 108792 (2022) - [j121]Masahiro Fujita, Yasuoki Iida, Mitsuhiro Hattori, Tadakazu Yamanaka, Nori Matsuda, Satoshi Ito, Hiroaki Kikuchi:
Proposal of anonymization dictionary using disclosed statements by business operators. Internet Things 18: 100490 (2022) - [j120]Mingfei Yu, Yukio Miyasaka, Masahiro Fujita:
Parallel Scheduling Attention Mechanism: Generalization and Optimization. IPSJ Trans. Syst. LSI Des. Methodol. 15: 2-15 (2022) - [j119]Binod Kumar, V. S. Vineesh, Puneet Nemade, Masahiro Fujita:
Aries: A Semiformal Technique for Fine-Grained Bug Localization in Hardware Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(12): 5709-5721 (2022) - [j118]Zolboo Byambadorj, Koji Asami, Takahiro J. Yamaguchi, Akio Higo, Masahiro Fujita, Tetsuya Iizuka:
High-Precision Sub-Nyquist Sampling System Based on Modulated Wideband Converter for Communication Device Testing. IEEE Trans. Circuits Syst. I Regul. Pap. 69(1): 378-388 (2022) - [j117]Ying Zhang, Yi Ding, Zebo Peng, Huawei Li, Masahiro Fujita, Jianhui Jiang:
BMC-Based Temperature-Aware SBST for Worst-Case Delay Fault Testing Under High Temperature. IEEE Trans. Very Large Scale Integr. Syst. 30(11): 1677-1690 (2022) - [c350]Utsav Jana, Sourav Banerjee, Binod Kumar, Madhu B, Shankar Umapathi, Masahiro Fujita:
Deep Learning-assisted Scan Chain Diagnosis with Different Fault Models during Manufacturing Test. ATS 2022: 72-77 - [c349]Ahmed Kiyoshi Sugihara, Takehisa Wada, Tamotsu Suda, Y. Nada, Masahiro Fujita, Shigeo Kawasaki, Osamu Mori:
A Single-Satellite Approach to Large Aperture Microwave Interferometric Radiometry Using Flexible Membrane Structures. IGARSS 2022: 7321-7324 - [c348]Xinpei Zhang, Yi Ding, Mingfei Yu, Shin-ichi O'Uchi, Masahiro Fujita:
Low-Precision Quantization Techniques for Hardware-Implementation-Friendly BERT Models. ISQED 2022: 1-6 - [c347]Jitendra Kumar, Asutosh Srivastava, Masahiro Fujita:
Formal Analysis of Integer Multipliers by building Binary Decision Diagram of Adder Trees. ISQED 2022: 58-63 - [c346]Shinnosuke Nozaki, Ayumi Serizawa, Mizuho Yoshihira, Masahiro Fujita, Yoichi Shibata, Tadakazu Yamanaka, Nori Matsuda, Tetsushi Ohki, Masakatsu Nishigaki:
Multi-observed Multi-factor Authentication: A Multi-factor Authentication Using Single Credential. NBiS 2022: 201-211 - [c345]Heming Sun, Qingyang Yi, Fangzheng Lin, Lu Yu, Jiro Katto, Masahiro Fujita:
Real-time Learned Image Codec on FPGA. VCIP 2022: 1 - [c344]Anishetti Venkatesh, Chandan Kumar Jha, G. U. Vinod, Masahiro Fujita, Virendra Singh:
Scalable Construction of Formal Error Guaranteed LUT-Based Approximate Multipliers with Analytical Worst-Case Error Bound. VDAT 2022: 397-407 - [c343]Pooja Choudhary, Lava Bhargava, Masahiro Fujita, Virendra Singh:
Synthesis of LUT Based Approximating Adder Circuits with Formal Error Guarantees. VDAT 2022: 435-449 - 2021
- [j116]Hari Mohan Gaur, Ashutosh Kumar Singh, Anand Mohan, Masahiro Fujita, Dhiraj K. Pradhan:
Design of Single-Bit Fault-Tolerant Reversible Circuits. IEEE Des. Test 38(2): 89-96 (2021) - [j115]He-Teng Zhang, Masahiro Fujita, Chung-Kuan Cheng, Jie-Hong R. Jiang:
SAT-Based On-Track Bus Routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(4): 735-747 (2021) - [j114]V. S. Vineesh, Binod Kumar, Rushikesh Shinde, Neelam Sharma, Masahiro Fujita, Virendra Singh:
Enhanced Design Debugging With Assistance From Guidance-Based Model Checking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(5): 985-998 (2021) - [c342]Mingfei Yu, Ruitao Gao, Masahiro Fujita:
A Decomposition-Based Synthesis Algorithm for Sparse Matrix-Vector Multiplication in Parallel Communication Structure. ASP-DAC 2021: 518-523 - [c341]Shubham Rai, Walter Lau Neto, Yukio Miyasaka, Xinpei Zhang, Mingfei Yu, Qingyang Yi, Masahiro Fujita, Guilherme B. Manske, Matheus F. Pontes, Leomar S. da Rosa, Marilton S. de Aguiar, Paulo F. Butzen, Po-Chun Chien, Yu-Shan Huang, Hoa-Ren Wang, Jie-Hong R. Jiang, Jiaqi Gu, Zheng Zhao, Zixuan Jiang, David Z. Pan, Brunno A. Abreu, Isac de Souza Campos, Augusto Andre Souza Berndt, Cristina Meinhardt, Jônata Tyska Carvalho, Mateus Grellert, Sergio Bampi, Aditya Lohana, Akash Kumar, Wei Zeng, Azadeh Davoodi, Rasit Onur Topaloglu, Yuan Zhou, Jordan Dotzel, Yichi Zhang, Hanyu Wang, Zhiru Zhang, Valerio Tenace, Pierre-Emmanuel Gaillardon, Alan Mishchenko, Satrajit Chatterjee:
Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization. DATE 2021: 1026-1031 - [c340]Yukio Miyasaka, Xinpei Zhang, Mingfei Yu, Qingyang Yi, Masahiro Fujita:
Logic Synthesis for Generalization and Learning Addition. DATE 2021: 1032-1037 - [c339]Masahiro Fujita, Yasuoki Iida, Mitsuhiro Hattori, Tadakazu Yamanaka, Nori Matsuda, Satoshi Ito, Hiroaki Kikuchi:
Proposal and Development of Anonymization Dictionary Using Public Information Disclosed by Anonymously Processed Information Handling Business Operators. IMIS 2021: 30-39 - [c338]Hiroaki Kikuchi, Atsuki Ono, Satoshi Ito, Masahiro Fujita, Tadakazu Yamanaka:
Web Crawler for an Anonymously Processed Information Database. IMIS 2021: 501-510 - [c337]Ryogo Koikel, Masahiro Fujita:
Efficient Reachability Analysis Based on Inductive Invariant Using X-value Based Flipflop Selection. ISQED 2021: 34-40 - [i5]Qingyang Yi, Heming Sun, Masahiro Fujita:
FPGA Based Accelerator for Neural Networks Computation with Flexible Pipelining. CoRR abs/2112.15443 (2021) - 2020
- [j113]Motoyasu Tanaka, Kazuyuki Kon, Mizuki Nakajima, Nobutaka Matsumoto, Shinnosuke Fukumura, Kosuke Fukui, Hidemasa Sawabe, Masahiro Fujita, Kenjiro Tadakuma:
Development and field test of the articulated mobile robot T2 Snake-4 for plant disaster prevention. Adv. Robotics 34(2): 70-88 (2020) - [j112]Nobutaka Matsumoto, Motoyasu Tanaka, Mizuki Nakajima, Masahiro Fujita, Kenjiro Tadakuma:
Development of a folding arm on an articulated mobile robot for plant disaster prevention. Adv. Robotics 34(2): 89-103 (2020) - [j111]Masahiro Fujita, Yukiyasu Domae, Akio Noda, Gustavo Alfonso Garcia Ricardez, Tatsuya Nagatani, Andy Zeng, Shuran Song, Alberto Rodriguez, Albert J. Causo, I-Ming Chen, Tsukasa Ogasawara:
What are the important technologies for bin picking? Technology analysis of robots in competitions based on a set of performance metrics. Adv. Robotics 34(7-8): 560-574 (2020) - [j110]Kenji Ono, Jorji Nonaka, Tomohiro Kawanabe, Masahiro Fujita, Kentaro Oku, Kazuma Hatta:
HIVE: A cross-platform, modular visualization framework for large-scale data sets. Future Gener. Comput. Syst. 112: 875-883 (2020) - [j109]Yukio Miyasaka, Akihiro Goda, Ashish Mittal, Masahiro Fujita:
Synthesis and Generalization of Parallel Algorithm for Matrix-vector Multiplication. IPSJ Trans. Syst. LSI Des. Methodol. 13: 31-34 (2020) - [j108]Peikun Wang, Amir Masoud Gharehbaghi, Masahiro Fujita:
A Logic Optimization Method by Eliminating Redundant Multiple Faults from Higher to Lower Cardinality. IPSJ Trans. Syst. LSI Des. Methodol. 13: 35-38 (2020) - [j107]Binod Kumar, Kanad Basu, Masahiro Fujita, Virendra Singh:
Post-Silicon Gate-Level Error Localization With Effective and Combined Trace Signal Selection. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(1): 248-261 (2020) - [j106]Peikun Wang, Amir Masoud Gharehbaghi, Masahiro Fujita:
An Automatic Test Pattern Generation Method for Multiple Stuck-At Faults by Incrementally Extending the Test Patterns. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(10): 2990-2999 (2020) - [j105]Zolboo Byambadorj, Koji Asami, Takahiro J. Yamaguchi, Akio Higo, Masahiro Fujita, Tetsuya Iizuka:
Theoretical Analysis of Noise Figure for Modulated Wideband Converter. IEEE Trans. Circuits Syst. I Regul. Pap. 67-I(1): 298-308 (2020) - [j104]Zolboo Byambadorj, Koji Asami, Takahiro J. Yamaguchi, Akio Higo, Masahiro Fujita, Tetsuya Iizuka:
A Calibration Technique for Simultaneous Estimation of Actual Sensing Matrix Coefficients on Modulated Wideband Converters. IEEE Trans. Circuits Syst. 67-I(12): 5561-5573 (2020) - [j103]Binod Kumar, Jay Adhaduk, Kanad Basu, Masahiro Fujita, Virendra Singh:
A Methodology to Capture Fine-Grained Internal Visibility During Multisession Silicon Debug. IEEE Trans. Very Large Scale Integr. Syst. 28(4): 1002-1015 (2020) - [c336]Yuya Shiomi, Genki Sugimoto, Ayaka Sugimoto, Kota Uehara, Masahiro Fujita, Yuto Mano, Tetsushi Ohki, Masakatsu Nishigaki:
Micro Biometric Authentication Using Fingernail Surfaces: A Study of Practical Use. AINA 2020: 1330-1340 - [c335]Zolboo Byambadorj, Koji Asami, Takahiro J. Yamaguchi, Akio Higo, Masahiro Fujita, Tetsuya Iizuka:
Theoretical Analysis on Noise Performance of Modulated Wideband Converters for Analog Testing. ATS 2020: 1-6 - [c334]Vinod G. U, Vineesh V. S., Jaynarayan T. Tudu, Masahiro Fujita, Virendra Singh:
LUT-based Circuit Approximation with Targeted Error Guarantees. ATS 2020: 1-6 - [c333]Masahiro Fujita, Yusuke Kimura, Xingming Le, Yukio Miyasaka, Amir Masoud Gharehbaghi:
Synthesis and Optimization of Multiple Portions of Circuits for ECO based on Set-Covering and QBF Formulations. DATE 2020: 744-749 - [c332]Kamal Das, Shubhankar Majumdar, Soumen Moulik, Masahiro Fujita:
Real-Time Threshold-based Landslide Prediction System for Hilly Region using Wireless Sensor Networks. ICCE-TW 2020: 1-2 - [c331]Akihiro Goda, Yukio Miyasaka, Amir Masoud Gharehbaghi, Masahiro Fujita:
Synthesis and Generalization of Parallel Algorithms Considering Communication Constraints. ISQED 2020: 123-128 - [c330]Yukio Miyasaka, Masahiro Fujita:
SAT-Based Data-Flow Mapping Onto Array Processor. VLSI-SOC 2020: 22-27 - [c329]Yukio Miyasaka, Masahiro Fujita, Alan Mishchenko, John Wawrzynek:
SAT-Based Mapping of Data-Flow Graphs onto Coarse-Grained Reconfigurable Arrays. VLSI-SoC (Selected Papers) 2020: 113-131 - [c328]Binod Kumar, Swapniel Thakur, Kanad Basu, Masahiro Fujita, Virendra Singh:
A Low Overhead Methodology for Validating Memory Consistency Models in Chip Multiprocessors. VLSID 2020: 101-106 - [i4]Mingfei Yu, Masahiro Fujita:
Parallel Scheduling Self-attention Mechanism: Generalization and Optimization. CoRR abs/2012.01114 (2020) - [i3]Shubham Rai, Walter Lau Neto, Yukio Miyasaka, Xinpei Zhang, Mingfei Yu, Qingyang Yi, Masahiro Fujita, Guilherme B. Manske, Matheus F. Pontes, Leomar S. da Rosa Jr., Marilton S. de Aguiar, Paulo F. Butzen, Po-Chun Chien, Yu-Shan Huang, Hoa-Ren Wang, Jie-Hong R. Jiang, Jiaqi Gu, Zheng Zhao, Zixuan Jiang, David Z. Pan, Brunno A. Abreu, Isac de Souza Campos, Augusto Andre Souza Berndt, Cristina Meinhardt, Jônata Tyska Carvalho, Mateus Grellert, Sergio Bampi, Aditya Lohana, Akash Kumar, Wei Zeng, Azadeh Davoodi, Rasit Onur Topaloglu, Yuan Zhou, Jordan Dotzel, Yichi Zhang, Hanyu Wang, Zhiru Zhang, Valerio Tenace, Pierre-Emmanuel Gaillardon, Alan Mishchenko, Satrajit Chatterjee:
Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization. CoRR abs/2012.02530 (2020)
2010 – 2019
- 2019
- [j102]Binod Kumar, Masahiro Fujita, Virendra Singh:
SAT-based Silicon Debug of Electrical Errors under Restricted Observability Enhancement. J. Electron. Test. 35(5): 655-678 (2019) - [j101]Yusuke Kimura, Amir Masoud Gharehbaghi, Masahiro Fujita:
Signal Selection Methods for Debugging Gate-Level Sequential Circuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 102-A(12): 1770-1780 (2019) - [j100]Masoud Shiroei, Bijan Alizadeh, Masahiro Fujita:
Data-path aware high-level ECO synthesis. Integr. 65: 88-96 (2019) - [j99]Heming Sun, Zhengxue Cheng, Amir Masoud Gharehbaghi, Shinji Kimura, Masahiro Fujita:
Approximate DCT Design for Video Encoding Based on Novel Truncation Scheme. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(4): 1517-1530 (2019) - [j98]Motoyasu Tanaka, Kenjiro Tadakuma, Mizuki Nakajima, Masahiro Fujita:
Task-Space Control of Articulated Mobile Robots With a Soft Gripper for Operations. IEEE Trans. Robotics 35(1): 135-146 (2019) - [c327]Kota Uehara, Kohei Mukaiyama, Masahiro Fujita, Hiroki Nishikawa, Takumi Yamamoto, Kiyoto Kawauchi, Masakatsu Nishigaki:
Basic Study on Targeted E-mail Attack Method Using OSINT. AINA 2019: 1329-1341 - [c326]Binod Kumar, Atul Kumar Bhosale, Masahiro Fujita, Virendra Singh:
Validating Multi-Processor Cache Coherence Mechanisms under Diminished Observability. ATS 2019: 99-104 - [c325]Masahiro Fujita, Yukiyasu Domae, Ryosuke Kawanishi, Gustavo Alfonso Garcia Ricardez, Kenta Kato, Koji Shiratsuchi, Rintaro Haraguchi, Ryosuke Araki, Hironobu Fujiyoshi, Shuichi Akizuki, Manabu Hashimoto, Albert J. Causo, Akio Noda, Haruhisa Okuda, Tsukasa Ogasawara:
Bin-picking Robot using a Multi-gripper Switching Strategy based on Object Sparseness. CASE 2019: 1540-1547 - [c324]Satyadev Ahlawat, Jaynarayan T. Tudu, Manoj Singh Gaur, Masahiro Fujita, Virendra Singh:
Preventing Scan Attack through Test Response Encryption. DFT 2019: 1-6 - [c323]Satyadev Ahlawat, Kailash Ahirwar, Jaynarayan T. Tudu, Masahiro Fujita, Virendra Singh:
Securing Scan through Plain-text Restriction. IOLTS 2019: 251-252 - [c322]Yusuke Kimura, Amir Masoud Gharehbaghi, Masahiro Fujita:
Signal Selection Methods for Efficient Multi-Target Correction. ISCAS 2019: 1-5 - [c321]Tomohiro Maruoka, Yukio Miyasaka, Akihiro Goda, Amir Masoud Gharehbaghi, Masahiro Fujita:
Live Demonstration: Automatic Synthesis of Algorithms on Multi Chip/FPGA with Communication Constraints. ISCAS 2019: 1 - [c320]Qinhao Wang, Amir Masoud Gharehbaghi, Takeshi Matsumoto, Masahiro Fujita:
High-Level Engineering Change Through Programmable Datapath and SMT Solvers. ISCAS 2019: 1-5 - [c319]Masahiro Fujita:
Basic and Advanced Researches in Logic Synthesis and their Industrial Contributions. ISPD 2019: 109-116 - [c318]Yukio Miyasaka, Ashish Mittal, Masahiro Fujita:
Synthesis of Algorithm Considering Communication Structure of Distributed/Parallel Computing. ISQED 2019: 45-51 - [c317]Peikun Wang, Amir Masoud Gharehbaghi, Masahiro Fujita:
Automatic Test Pattern Generation for Double Stuck-at Faults Based on Test Patterns of Single Faults. ISQED 2019: 284-290 - [c316]Masahiro Fujita:
AI x Robotics: Technology Challenges and Opportunities in Sensors, Actuators, and Integrated Circuits. ISSCC 2019: 276-278 - [c315]Mayank Palaria, Sai Sanjeet, Bibhu Datta Sahoo, Masahiro Fujita:
Adder-Only Convolutional Neural Network with Binary Input Image. MWSCAS 2019: 319-322 - [c314]Qi Lu, Amir Masoud Gharehbaghi, Masahiro Fujita:
Approximate Arithmetic Circuit Design Using a Fast and Scalable Method. VLSI-SoC 2019: 65-70 - [c313]Takahiko Ishizu, Yuto Yakubo, Kazuma Furutani, Atsuo Isobe, Masashi Fujita, Tomoaki Atsumi, Yoshinori Ando, Tsutomu Murakawa, Kiyoshi Kato, Masahiro Fujita, Shunpei Yamazaki:
A 48 MHz 880-nW Standby Power Normally-Off MCU with 1 Clock Full Backup and 4.69-μs Wakeup Featuring 60-nm Crystalline In-Ga-Zn Oxide BEOL-FETs. VLSI Circuits 2019: 48- - [c312]Binod Kumar, Masahiro Fujita, Virendra Singh:
A Methodology for SAT-Based Electrical Error Debugging During Post-Silicon Validation. VLSID 2019: 389-394 - [c311]Peikun Wang, Amir Masoud Gharehbaghi, Masahiro Fujita:
An Incremental Automatic Test Pattern Generation Method for Multiple Stuck-at Faults. VTS 2019: 1-6 - [p1]Fumitoshi Matsuno, Tetsushi Kamegawa, Wei Qi, Tatsuya Takemori, Motoyasu Tanaka, Mizuki Nakajima, Kenjiro Tadakuma, Masahiro Fujita, Yosuke Suzuki, Katsutoshi Itoyama, Hiroshi G. Okuno, Yoshiaki Bando, Tomofumi Fujiwara, Satoshi Tadokoro:
Development of Tough Snake Robot Systems. Disaster Robotics 2019: 267-326 - [e2]Nicola Bombieri, Graziano Pravadelli, Masahiro Fujita, Todd M. Austin, Ricardo Reis:
VLSI-SoC: Design and Engineering of Electronics Systems Based on New Computing Paradigms - 26th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2018, Verona, Italy, October 8-10, 2018, Revised and Extended Selected Papers. IFIP Advances in Information and Communication Technology 561, Springer 2019, ISBN 978-3-030-23424-9 [contents] - 2018
- [j97]Masahiro Fujita, Suguru Ikeda, Toshiaki Fujimoto, Toshihiko Shimizu, Shuhei Ikemoto, Takeshi Miyamoto:
Development of universal vacuum gripper for wall-climbing robot. Adv. Robotics 32(6): 283-296 (2018) - [j96]Masahiro Fujita, Kenjiro Tadakuma, Hirone Komatsu, Eri Takane, Akito Nomura, Tomoya Ichimura, Masashi Konyo, Satoshi Tadokoro:
Jamming layered membrane gripper mechanism for grasping differently shaped-objects without excessive pushing force for search and rescue missions. Adv. Robotics 32(11): 590-604 (2018) - [j95]Toral Shah, Anzhela Yu. Matrosova, Masahiro Fujita, Virendra Singh:
Multiple Stuck-at Fault Testability Analysis of ROBDD Based Combinational Circuit Design. J. Electron. Test. 34(1): 53-65 (2018) - [j94]Jorji Nonaka, Kenji Ono, Masahiro Fujita:
234Compositor: A flexible parallel image compositing framework for massively parallel visualization environments. Future Gener. Comput. Syst. 82: 647-655 (2018) - [j93]Yusuke Kimura, Amir Masoud Gharehbaghi, Masahiro Fujita:
C Description Reconstruction Method from a Revised Netlist for ECO Support. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 101-A(4): 685-696 (2018) - [j92]Kenjiro Tadakuma, Eri Takane, Masahiro Fujita, Akito Nomura, Hirone Komatsu, Masashi Konyo, Satoshi Tadokoro:
Planar Omnidirectional Crawler Mobile Mechanism - Development of Actual Mechanical Prototype and Basic Experiments. IEEE Robotics Autom. Lett. 3(1): 395-402 (2018) - [j91]Hiroyuki Suzuki, Hiromasa Masuda, Kazuo Hongo, Ryuta Horie, Shunsuke Yajima, Yuki Itotani, Masahiro Fujita, Ken'ichiro Nagasaka:
Development and Testing of Force-Sensing Forceps Using FBG for Bilateral Micro-Operation System. IEEE Robotics Autom. Lett. 3(4): 4281-4288 (2018) - [j90]Peikun Wang, Conrad J. Moore, Amir Masoud Gharehbaghi, Masahiro Fujita:
An ATPG Method for Double Stuck-At Faults by Analyzing Propagation Paths of Single Faults. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(3): 1063-1074 (2018) - [c310]Jorji Nonaka, Motohiko Matsuda, Takashi Shimizu, Naohisa Sakamoto, Masahiro Fujita, Keiji Onishi, Eduardo C. Inacio, Shun Ito, Fumiyoshi Shoji, Kenji Ono:
A Study on Open Source Software for Large-Scale Data Visualization on SPARC64fx based HPC Systems. HPC Asia 2018: 278-288 - [c309]Genki Sugimoto, Masahiro Fujita, Yuto Mano, Tetsushi Ohki, Masakatsu Nishigaki:
Micro Disposable Biometric Authentication: An Application Using Fingernail Minute Textures for Nonsensitive Services. ICBSP 2018: 68-73 - [c308]Amir Masoud Gharehbaghi, Tomohiro Maruoka, Masahiro Fujita:
A New Reconfigurable Architecture with Applications to IoT and Mobile Computing. IFIPIoT@WCC 2018: 133-146 - [c307]Darshit Vaghani, Satyadev Ahlawat, Jaynarayan T. Tudu, Masahiro Fujita, Virendra Singh:
On Securing Scan Design Through Test Vector Encryption. ISCAS 2018: 1-5 - [c306]Shuhei Maeda, Satoru Ohshita, Kazuma Furutani, Yuto Yakubo, Takahiko Ishizu, Tomoaki Atsumi, Yoshinori Ando, Daisuke Matsubayashi, Kiyoshi Kato, Takashi Okuda, Masahiro Fujita, Shunpei Yamazaki:
A 20ns-write 45ns-read and 1014-cycle endurance memory module composed of 60nm crystalline oxide semiconductor transistors. ISSCC 2018: 484-486 - [c305]Ankit Jindal, Binod Kumar, Nitish Jindal, Masahiro Fujita, Virendra Singh:
Silicon Debug with Maximally Expanded Internal Observability Using Nearest Neighbor Algorithm. ISVLSI 2018: 46-51 - [c304]Jorji Nonaka, Kenji Ono, Naohisa Sakamoto, Kengo Hayashi, Motohiko Matsuda, Fumiyoshi Shoji, Kentaro Oku, Masahiro Fujita, Kazuma Hatta:
A Large Data Visualization Framework for SPARC64 fx HPC Systems - Case Study: K Computer Operational Environment -. LDAV 2018: 108-109 - [c303]Antara Ganguly, Virendra Singh, Rajeev Muralidhar, Masahiro Fujita:
Memory-system requirements for convolutional neural networks. MEMSYS 2018: 291-197 - [c302]Ankit Jindal, Binod Kumar, Kanad Basu, Masahiro Fujita:
ELURA: A Methodology for Post-Silicon Gate-Level Error Localization Using Regression Analysis. VLSID 2018: 410-415 - 2017
- [j89]Tatsuya Onuki, Wataru Uesugi, Atsuo Isobe, Yoshinori Ando, Satoru Okamoto, Kiyoshi Kato, Tri Rung Yew, J. Y. Wu, Chi Chang Shuai, Shao Hui Wu, James Myers, Klaus Doppler, Masahiro Fujita, Shunpei Yamazaki:
Embedded Memory and ARM Cortex-M0 Core Using 60-nm C-Axis Aligned Crystalline Indium-Gallium-Zinc Oxide FET Integrated With 65-nm Si CMOS. IEEE J. Solid State Circuits 52(4): 925-932 (2017) - [j88]Munehiro Kozuma, Yuki Okamoto, Takashi Nakagawa, Takeshi Aoki, Yoshiyuki Kurokawa, Takayuki Ikeda, Yoshinori Ieda, Naoto Yamade, Hidekazu Miyairi, Makoto Ikeda, Masahiro Fujita, Shunpei Yamazaki:
Subthreshold Operation of CAAC-IGZO FPGA by Overdriving of Programmable Routing Switch and Programmable Power Switch. IEEE Trans. Very Large Scale Integr. Syst. 25(1): 125-138 (2017) - [c301]Kentaro Iwata, Amir Masoud Gharehbaghi, Mehdi Baradaran Tahoori, Masahiro Fujita:
Post Silicon Debugging of Electrical Bugs Using Trace Buffers. ATS 2017: 189-194 - [c300]Ayane Sano, Masahiro Fujita, Masakatsu Nishigaki:
Directcha-maze: A Study of CAPTCHA Configuration with Machine Learning and Brute-Force Attack Defensibility Along with User Convenience Consideration. BWCCA 2017: 489-501 - [c299]Ryohei Banno, Jingyu Sun, Masahiro Fujita, Susumu Takeuchi, Kazuyuki Shudo:
Dissemination of edge-heavy data on heterogeneous MQTT brokers. CloudNet 2017: 5-11 - [c298]Shintaro Ishihara, Masahiro Fujita, Toyokazu Akiyama:
DNetSpec: A Distributed Network Testing Toolset for Middleware Developers. COMPSAC (2) 2017: 1-6 - [c297]Binod Kumar, Ankit Jindal, Masahiro Fujita, Virendra Singh:
Combining Restorability and Error Detection Ability for Effective Trace Signal Selection. ACM Great Lakes Symposium on VLSI 2017: 191-196 - [c296]Binod Kumar, Kanad Basu, Masahiro Fujita, Virendra Singh:
RTL level trace signal selection and coverage estimation during post-silicon validation. HLDVT 2017: 59-66 - [c295]Masahiro Fujita:
An approach to approximate computing: Logic transformations for one-minterm changes in specification. HLDVT 2017: 91-94 - [c294]Jorji Nonaka, Naohisa Sakamoto, Takashi Shimizu, Masahiro Fujita, Kenji Ono, Koji Koyamada:
Distributed Particle-Based Rendering Framework for Large Data Visualization on HPC Environments. HPCS 2017: 300-307 - [c293]Nihar Hage, Rohini Gulve, Masahiro Fujita, Virendra Singh:
Instruction-based self-test for delay faults maximizing operating temperature. IOLTS 2017: 259-264 - [c292]Amir Masoud Gharehbaghi, Masahiro Fujita:
A new approach for diagnosing bridging faults in logic designs. ISCAS 2017: 1-4 - [c291]Conrad J. Moore, Peikun Wang, Amir Masoud Gharehbaghi, Masahiro Fujita:
Test pattern generation for multiple stuck-at faults not covered by test patterns for single faults. ISCAS 2017: 1-4 - [c290]Heming Sun, Zhengxue Cheng, Amir Masoud Gharehbaghi, Shinji Kimura, Masahiro Fujita:
A low-cost approximate 32-point transform architecture. ISCAS 2017: 1-4 - [c289]Amir Masoud Gharehbaghi, Masahiro Fujita:
A new approach for selecting inputs of logic functions during debug. ISQED 2017: 166-173 - [c288]Sahand Salamat, Mehrnaz Ahmadi, Bijan Alizadeh, Masahiro Fujita:
Systematic approximate logic optimization using don't care conditions. ISQED 2017: 419-425 - [c287]Qinhao Wang, Yusuke Kimura, Masahiro Fujita:
Methods of equivalence checking and ECO support under C-based design through reproduction of C descriptions from implementation designs. ISQED 2017: 432-437 - [c286]Binod Kumar, Ankit Jindal, Masahiro Fujita, Virendra Singh:
Post-silicon observability enhancement with topology based trace signal selection. LATS 2017: 1-6 - [c285]Toral Shah, Anzhela Yu. Matrosova, Binod Kumar, Masahiro Fujita, Virendra Singh:
Testing multiple stuck-at faults of ROBDD based combinational circuit design. LATS 2017: 1-6 - [c284]Kohei Mukaiyama, Masahiro Fujita, Takeharu Shirai, Shinya Kobayashi, Masakatsu Nishigaki:
Slyware Prevention: Threat of Websites Inducing Accidental Taps and Countermeasures. NBiS 2017: 539-552 - [c283]Binod Kumar, Kanad Basu, Ankit Jindal, Brajesh Pandey, Masahiro Fujita:
A Formal Perspective on Effective Post-silicon Debug and Trace Signal Selection. VDAT 2017: 753-766 - [c282]Binod Kumar, Kanad Basu, Ankit Jindal, Masahiro Fujita, Virendra Singh:
Improving post-silicon error detection with topological selection of trace signals. VLSI-SoC 2017: 1-6 - [c281]Masahiro Fujita, Yusuke Kimura, Qinhao Wang:
Template based synthesis for high performance computing. VLSI-SoC 2017: 1-6 - [c280]Amir Masoud Gharehbaghi, Masahiro Fujita:
A new approach for constructing logic functions after ECO. VLSI-SoC 2017: 1-6 - [c279]Binod Kumar, Ankit Jindal, Virendra Singh, Masahiro Fujita:
A Methodology for Trace Signal Selection to Improve Error Detection in Post-Silicon Validation. VLSID 2017: 147-152 - [c278]Nihar Hage, Rohini Gulve, Masahiro Fujita, Virendra Singh:
On Testing of Superscalar Processors in Functional Mode for Delay Faults. VLSID 2017: 397-402 - 2016
- [j87]Amir Masoud Gharehbaghi, Masahiro Fujita:
Fast and Efficient Signature-Based Sub-Circuit Matching. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 99-A(7): 1355-1365 (2016) - [c277]Payman Behnam, Bijan Alizadeh, Sajjad Taheri, Masahiro Fujita:
Formally analyzing fault tolerance in datapath designs using equivalence checking. ASP-DAC 2016: 133-138 - [c276]Amir Masoud Gharehbaghi, Masahiro Fujita:
A New Approach for Debugging Logic Circuits without Explicitly Debugging Their Functionality. ATS 2016: 31-36 - [c275]Masahiro Fujita:
Synthesizing and Completely Testing Hardware Based on Templates Through Small Numbers of Test Patterns. ATVA 2016: 3-10 - [c274]Takashi Tsuchiya, Masahiro Fujita, Kenta Takahashi, Takehisa Kato, Fumihiko Magata, Yoshimi Teshigawara, Ryôichi Sasaki, Masakatsu Nishigaki:
Secure Communication Protocol Between a Human and a Bank Server for Preventing Man-in-the-Browser Attacks. HCI (20) 2016: 77-88 - [c273]Masahiro Fujita, Mako Yamada, Masakatsu Nishigaki:
Implementation and Initial Evaluation of Game in Which Password Enhancement Factor is Embedded. HCI (26) 2016: 476-481 - [c272]Yusuke Kimura, Masahiro Fujita:
Specification by existing design plus use-cases. HLDVT 2016: 40-45 - [c271]Qinhao Wang, Yusuke Kimura, Masahiro Fujita:
Automatically adjusting system level designs after RTL/gate-level ECO. HLDVT 2016: 108-112 - [c270]Masahiro Fujita, Yuto Mano, Takuya Kaneko, Kenta Takahashi, Masakatsu Nishigaki:
A Micro Biometric Authentication Mechanism Considering Minute Patterns of the Human Body: A Proposal and the First Attempt. NBiS 2016: 159-164 - [c269]Takeharu Shirai, Masahiro Fujita, Daisuke Arai, Tomohiko Ogishi, Masakatsu Nishigaki:
Study on relationship between user awareness and QoE in communication delay on smartphones. PST 2016: 573-580 - [c268]Ayane Sano, Masahiro Fujita, Masakatsu Nishigaki:
Directcha: A proposal of spatiometric mental rotation CAPTCHA. PST 2016: 585-592 - [c267]Eri Takane, Kenjiro Tadakuma, Masahiro Fujita, Hirone Komatsu, Akito Nomura, Tomoya Ichimura, Tomonari Yamamoto, Yuichi Ambe, Masashi Konyo, Satoshi Tadokoro:
Two axes orthogonal drive transmission for omnidirectional crawler with surface contact. SSRR 2016: 378-383 - [c266]Masahiro Fujita, Kenjiro Tadakuma, Eri Takane, Tomoya Ichimura, Hirone Komatsu, Akito Nomura, Masashi Konyo, Satoshi Tadokoro:
Variable inner volume mechanism for soft and robust gripping - Improvement of gripping performance for large-object gripping. SSRR 2016: 390-395 - [c265]Tatsuya Onuki, Wataru Uesugi, Hikaru Tamura, Atsuo Isobe, Yoshinori Ando, Satoru Okamoto, Kiyoshi Kato, Tri Rung Yew, Chen Bin Lin, J. Y. Wu, Chi Chang Shuai, Shao Hui Wu, James Myers, Klaus Doppler, Masahiro Fujita, Shunpei Yamazaki:
Embedded memory and ARM Cortex-M0 core using 60-nm C-axis aligned crystalline indium-gallium-zinc oxide FET integrated with 65-nm Si CMOS. VLSI Circuits 2016: 1-2 - 2015
- [j86]Masahiro Fujita, Osamu Koike, Yukio Yamaguchi:
Direct simulation of drying colloidal suspension on substrate using immersed free surface model. J. Comput. Phys. 281: 421-448 (2015) - [j85]Takeshi Aoki, Yuki Okamoto, Takashi Nakagawa, Munehiro Kozuma, Yoshiyuki Kurokawa, Takayuki Ikeda, Naoto Yamade, Yutaka Okazaki, Hidekazu Miyairi, Masahiro Fujita, Jun Koyama, Shunpei Yamazaki:
Normally-Off Computing for Crystalline Oxide Semiconductor-Based Multicontext FPGA Capable of Fine-Grained Power Gating on Programmable Logic Element With Nonvolatile Shadow Register. IEEE J. Solid State Circuits 50(9): 2199-2211 (2015) - [j84]Masahiro Fujita:
Toward Unification of Synthesis and Verification in Topologically Constrained Logic Design. Proc. IEEE 103(11): 2052-2060 (2015) - [j83]Samaneh Ghandali, Bijan Alizadeh, Masahiro Fujita, Zainalabedin Navabi:
Automatic High-Level Data-Flow Synthesis and Optimization of Polynomial Datapaths Using Functional Decomposition. IEEE Trans. Computers 64(6): 1579-1593 (2015) - [j82]Yuki Okamoto, Takashi Nakagawa, Takeshi Aoki, Masataka Ikeda, Munehiro Kozuma, Takeshi Osada, Yoshiyuki Kurokawa, Takayuki Ikeda, Naoto Yamade, Yutaka Okazaki, Hidekazu Miyairi, Masahiro Fujita, Jun Koyama, Shunpei Yamazaki:
A Boosting Pass Gate With Improved Switching Characteristics and No Overdriving for Programmable Routing Switch Based on Crystalline In-Ga-Zn-O Technology. IEEE Trans. Very Large Scale Integr. Syst. 23(3): 422-434 (2015) - [c264]Masahiro Fujita:
Detection of test Patterns with Unreachable States through Efficient Inductive-Invariant Identification. ATS 2015: 31-36 - [c263]Ying Zhang, Zebo Peng, Jianhui Jiang, Huawei Li, Masahiro Fujita:
Temperature-aware software-based self-testing for delay faults. DATE 2015: 423-428 - [c262]Masahiro Fujita:
On Implementation of LUT with Large Numbers of Inputs (Abstract Only). FPGA 2015: 277 - [c261]Masahiro Fujita, Yuki Ikeya, Junya Kani, Masakatsu Nishigaki:
Chimera CAPTCHA: A Proposal of CAPTCHA Using Strangeness in Merged Objects. HCI (22) 2015: 48-58 - [c260]Masahiro Fujita:
Automatic identification of assertions and invariants with small numbers of test vectors. ICCD 2015: 463-466 - [c259]Jorji Nonaka, Kenji Ono, Masahiro Fujita:
234 scheduling of 3-2 and 2-1 eliminations for parallel image compositing using non-power-of-two number of processes. HPCS 2015: 421-428 - [c258]Masahiro Fujita, Naoki Taguchi, Kentaro Iwata, Alan Mishchenko:
Incremental ATPG methods for multiple faults under multiple fault models. ISQED 2015: 177-180 - [c257]Takanori Matsuzaki, Tatsuya Onuki, Shuhei Nagatsuka, Hiroki Inoue, Takahiko Ishizu, Yoshinori Ieda, Naoto Yamade, Hidekazu Miyairi, Masayuki Sakakura, Tomoaki Atsumi, Yutaka Shionoiri, Kiyoshi Kato, Takashi Okuda, Yoshitaka Yamamoto, Masahiro Fujita, Jun Koyama, Shunpei Yamazaki:
16.9 A 128kb 4b/cell nonvolatile memory with crystalline In-Ga-Zn oxide FET using Vt, cancel write method. ISSCC 2015: 1-3 - [c256]Sriram Karunagaran, Karuna P. Sahoo, Masahiro Fujita:
Hardware in loop testing of an insulin pump. ITC 2015: 1-8 - [c255]Masahiro Fujita:
Logic analysis and optimization with quick identification of invariants through one time frame analysis. MEMOCODE 2015: 102-107 - [c254]Masahiro Fujita, Mako Yamada, Shiori Arimura, Yuki Ikeya, Masakatsu Nishigaki:
An Attempt to Memorize Strong Passwords while Playing Games. NBiS 2015: 264-268 - [c253]Masahiro Fujita, Christian Damsgaard Jensen, Shiori Arimura, Yuki Ikeya, Masakatsu Nishigaki:
Physical trust-based persistent authentication. PST 2015: 186-190 - [c252]Masahiro Fujita:
Analysis and testing on delays with two time frames. VLSI-SoC 2015: 13-18 - [c251]Masahiro Fujita:
Delay Testing Based on Multiple Faulty Behaviors. VLSI-SoC (Selected Papers) 2015: 87-108 - [c250]Shridhar Choudhary, Amir Masoud Gharehbaghi, Takeshi Matsumoto, Masahiro Fujita:
Trace signal selection methods for post silicon debugging. VLSI-SoC 2015: 258-263 - [c249]Amir Masoud Gharehbaghi, Masahiro Fujita:
Efficient signature-based sub-circuit matching. VLSI-SoC 2015: 280-285 - [c248]Reza Sharafinejad, Bijan Alizadeh, Masahiro Fujita:
UPF-based formal verification of low power techniques in modern processors. VTS 2015: 1-6 - 2014
- [j81]Amir Masoud Gharehbaghi, Masahiro Fujita:
Automatic Rectification of Processor Design Bugs Using a Scalable and General Correction Model. IEICE Trans. Inf. Syst. 97-D(4): 852-863 (2014) - [j80]Hiroaki Yoshida, Masayuki Wakizaka, Shigeru Yamashita, Masahiro Fujita:
An Energy-Efficient Patchable Accelerator and Its Design Methods. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(12): 2507-2517 (2014) - [j79]Satoshi Jo, Takeshi Matsumoto, Masahiro Fujita:
SAT-based Automatic Rectification and Debugging of Combinational Circuits with LUT Insertions. IPSJ Trans. Syst. LSI Des. Methodol. 7: 46-55 (2014) - [j78]Hikaru Tamura, Kiyoshi Kato, Takahiko Ishizu, Wataru Uesugi, Atsuo Isobe, Naoaki Tsutsui, Yasutaka Suzuki, Yutaka Okazaki, Yukio Maehashi, Jun Koyama, Yoshitaka Yamamoto, Shunpei Yamazaki, Masahiro Fujita, James Myers, Pekka Korpinen:
Embedded SRAM and Cortex-M0 Core Using a 60-nm Crystalline Oxide Semiconductor. IEEE Micro 34(6): 42-53 (2014) - [j77]Tetsuya Tsujikawa, Sami S. Zoghbi, Jinsoo Hong, Sean R. Donohue, Kimberly J. Jenko, Robert L. Gladding, Christer Halldin, Victor W. Pike, Robert B. Innis, Masahiro Fujita:
In vitro and in vivo evaluation of 11C-SD5024, a novel PET radioligand for human brain imaging of cannabinoid CB1 receptors. NeuroImage 84: 733-741 (2014) - [j76]Talakad G. Lohith, Sami S. Zoghbi, Cheryl L. Morse, Maria D. Ferraris Araneta, Vanessa N. Barth, Nancy A. Goebl, Johannes T. Tauscher, Victor W. Pike, Robert B. Innis, Masahiro Fujita:
Retest imaging of [11C]NOP-1A binding to nociceptin/orphanin FQ peptide (NOP) receptors in the brain of healthy humans. NeuroImage 87: 89-95 (2014) - [c247]Hikaru Tamura, Kiyoshi Kato, Takahiko Ishizu, Tatsuya Onuki, Wataru Uesugi, Takuro Ohmaru, Kazuaki Ohshima, Hidetomo Kobayashi, Seiichi Yoneda, Atsuo Isobe, Naoaki Tsutsui, Suguru Hondo, Yasutaka Suzuki, Yutaka Okazaki, Tomoaki Atsumi, Yutaka Shionoiri, Yukio Maehashi, Gensuke Goto, Masahiro Fujita, James Myers, Pekka Korpinen, Jun Koyama, Yoshitaka Yamamoto, Shunpei Yamazaki:
Embedded SRAM and Cortex-M0 core with backup circuits using a 60-nm crystalline oxide semiconductor for power gating. COOL Chips 2014: 1-3 - [c246]Somayeh Sadeghi Kohan, Payman Behnam, Bijan Alizadeh, Masahiro Fujita, Zainalabedin Navabi:
Improving polynomial datapath debugging with HEDs. ETS 2014: 1-6 - [c245]Yuki Ikeya, Masahiro Fujita, Junya Kani, Yuta Yoneyama, Masakatsu Nishigaki:
An Image-Based CAPTCHA Using Sophisticated Mental Rotation. HCI (24) 2014: 57-68 - [c244]Jorji Nonaka, Kenji Ono, Masahiro Fujita:
Multi-step image compositing for massively parallel rendering. HPCS 2014: 627-634 - [c243]Samaneh Ghandali, Bijan Alizadeh, Masahiro Fujita, Zainalabedin Navabi:
RTL datapath optimization using system-level transformations. ISQED 2014: 309-316 - [c242]Amir Masoud Gharehbaghi, Masahiro Fujita:
Specification and formal verification of power gating in processors. ISQED 2014: 604-610 - [c241]Takeshi Aoki, Yuki Okamoto, Takashi Nakagawa, Masataka Ikeda, Munehiro Kozuma, Takeshi Osada, Yoshiyuki Kurokawa, Takayuki Ikeda, Naoto Yamade, Yutaka Okazaki, Hidekazu Miyairi, Masahiro Fujita, Jun Koyama, Shunpei Yamazaki:
30.9 Normally-off computing with crystalline InGaZnO-based FPGA. ISSCC 2014: 502-503 - [c240]Masahiro Fujita:
Variation-Aware Analysis and Test Pattern Generation Based on Functional Faults. ISVLSI 2014: 273-277 - [c239]Masahiro Fujita, Alan Mishchenko:
Efficient SAT-based ATPG techniques for all multiple stuck-at faults. ITC 2014: 1-10 - [c238]Shiori Arimura, Masahiro Fujita, Shinya Kobayashi, Junya Kani, Masakatsu Nishigaki, Akira Shiba:
i/k-Contact: A context-aware user authentication using physical social trust. PST 2014: 407-413 - [c237]Sriram Karunagaran, Karuna P. Sahoo, Jayaraj Poroor, Masahiro Fujita:
MAESTRO: A time-driven embedded testbed Architecture with Event-driven Synchronization. RTAS 2014: 237-248 - [c236]Masahiro Fujita, Alan Mishchenko:
Logic synthesis and verification on fixed topology. VLSI-SoC 2014: 1-6 - [c235]Atsuo Isobe, Hikaru Tamura, Kiyoshi Kato, Takuro Ohmaru, Wataru Uesugi, Takahiko Ishizu, Tatsuya Onuki, Kazuaki Ohshima, Takanori Matsuzaki, Atsushi Hirose, Yasutaka Suzuki, Naoaki Tsutsui, Tomoaki Atsumi, Yutaka Shionoiri, Gensuke Goto, Jun Koyama, Masahiro Fujita, Shunpei Yamazaki:
A 32-bit CPU with zero standby power and 1.5-clock sleep/2.5-clock wake-up achieved by utilizing a 180-nm C-axis aligned crystalline In-Ga-Zn oxide transistor. VLSIC 2014: 1-2 - 2013
- [j75]Giuseppe Di Guglielmo, Luigi Di Guglielmo, Andreas Foltinek, Masahiro Fujita, Franco Fummi, Cristina Marconcini, Graziano Pravadelli:
On the integration of model-driven design and dynamic assertion-based verification for embedded software. J. Syst. Softw. 86(8): 2013-2033 (2013) - [c234]Satoshi Jo, Amir Masoud Gharehbaghi, Takeshi Matsumoto, Masahiro Fujita:
Rectification of advanced microprocessors without changing routing on FPGAs (abstract only). FPGA 2013: 279 - [c233]Satoshi Jo, Amir Masoud Gharehbaghi, Takeshi Matsumoto, Masahiro Fujita:
Debugging processors with advanced features by reprogramming LUTs on FPGA. FPT 2013: 50-57 - [c232]Will X. Y. Li, Shridhar Chaudhary, Ray C. C. Cheung, Takeshi Matsumoto, Masahiro Fujita:
Fast simulation of Digital Spiking Silicon Neuron model employing reconfigurable dataflow computing. FPT 2013: 478-479 - [c231]Kosuke Oshima, Takeshi Matsumoto, Masahiro Fujita:
Hardware implementation of BLTL property checkers for acceleration of statistical model checking. ICCAD 2013: 670-676 - [c230]Masahiro Fujita, Satoshi Jo, Shohei Ono, Takeshi Matsumoto:
Partial synthesis through sampling with and without specification. ICCAD 2013: 787-794 - [c229]Kosuke Oshima, Takeshi Matsumoto, Masahiro Fujita:
Debugging Methods Through Identification of Appropriate Functions for Internal Gates. VLSI-SoC (Selected Papers) 2013: 1-22 - [c228]Kosuke Oshima, Takeshi Matsumoto, Masahiro Fujita:
A debugging method for gate level circuit designs by introducing programmability. VLSI-SoC 2013: 78-83 - [c227]Masahiro Fujita, Takeshi Matsumoto, Satoshi Jo:
FOF: Functionally Observable Fault and its ATPG techniques. VLSI-SoC 2013: 108-111 - [c226]Prabhat Mishra, Masahiro Fujita, Virendra Singh, Nagesh Tamarapalli, Sharad Kumar, Rajesh Mittal:
Tutorial T10: Post - Silicon Validation, Debug and Diagnosis. VLSI Design 2013 - [c225]Jennifer Dworak, Ronald Shawn Blanton, Masahiro Fujita, Kazumi Hatayama, Naghmeh Karimi, Michail Maniatakos, Antonis M. Paschalis, Adit D. Singh, Tian Xia:
Special session 4B: Elevator talks. VTS 2013: 1 - 2012
- [j74]Viacheslav Izosimov, Giuseppe Di Guglielmo, Michele Lora, Graziano Pravadelli, Franco Fummi, Zebo Peng, Masahiro Fujita:
Time-Constraint-Aware Optimization of Assertions in Embedded Software. J. Electron. Test. 28(4): 469-486 (2012) - [j73]Amir Masoud Gharehbaghi, Masahiro Fujita:
Transaction Ordering in Network-on-Chips for Post-Silicon Validation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 95-A(12): 2309-2318 (2012) - [j72]Yasuyuki Kimura, Fabrice G. Siméon, Sami S. Zoghbi, Yi Zhang, Jun Hatazawa, Victor W. Pike, Robert B. Innis, Masahiro Fujita:
Quantification of metabotropic glutamate subtype 5 receptors in the brain by an equilibrium method using 18F-SP203. NeuroImage 59(3): 2124-2130 (2012) - [j71]Paolo Zanotti-Fregonara, Christina S. Hines, Sami S. Zoghbi, Jeih-San Liow, Yi Zhang, Victor W. Pike, Wayne C. Drevets, Alan G. Mallinger, Carlos A. Zarate Jr., Masahiro Fujita, Robert B. Innis:
Population-based input function and image-derived input function for [11C](R)-rolipram PET imaging: Methodology, validation and application to the study of major depressive disorder. NeuroImage 63(3): 1532-1541 (2012) - [c224]Masahiro Fujita, Hiroaki Yoshida:
Post-silicon patching for verification/debugging with high-level models and programmable logic. ASP-DAC 2012: 232-237 - [c223]Yu-Shen Yang, Andreas G. Veneris, Nicola Nicolici, Masahiro Fujita:
Automated data analysis techniques for a modern silicon debug environment. ASP-DAC 2012: 298-303 - [c222]Hratch Mangassarian, Hiroaki Yoshida, Andreas G. Veneris, Shigeru Yamashita, Masahiro Fujita:
On error tolerance and Engineering Change with Partially Programmable Circuits. ASP-DAC 2012: 695-700 - [c221]Satoshi Jo, Takeshi Matsumoto, Masahiro Fujita:
SAT-Based Automatic Rectification and Debugging of Combinational Circuits with LUT Insertions. Asian Test Symposium 2012: 19-24 - [c220]Amir Masoud Gharehbaghi, Masahiro Fujita:
Error Model Free Automatic Design Error Correction of Complex Processors Using Formal Methods. Asian Test Symposium 2012: 143-148 - [c219]Marco Bonato, Giuseppe Di Guglielmo, Masahiro Fujita, Franco Fummi, Graziano Pravadelli:
Dynamic property mining for embedded software. CODES+ISSS 2012: 187-196 - [c218]Masahiro Fujita:
Simulation-Based Analysis of Cyberphysical Systems. DSD 2012: 485-492 - [c217]Masahiro Fujita, Hiroaki Yoshida:
Post-silicon debugging targeting electrical errors with patchable controllers (abstract only). FPGA 2012: 271 - [c216]Amir Masoud Gharehbaghi, Masahiro Fujita:
Automatic rectification of design errors in complex processors with programmable hardware. FPT 2012: 141-146 - [c215]Bijan Alizadeh, Masahiro Fujita:
A functional test generation technique for RTL datapaths. HLDVT 2012: 64-70 - [c214]Masahiro Fujita:
Post-silicon verification and debugging with control flow traces and patchable hardware. HLDVT 2012: 100-107 - [c213]Shohei Ono, Takeshi Matsumoto, Masahiro Fujita:
Automatic assertion extraction in gate-level simulation using GPGPUs. ICCD 2012: 522-523 - [c212]Mohammed Shayan, Virendra Singh, Adit D. Singh, Masahiro Fujita:
SEU tolerant robust memory cell design. IOLTS 2012: 13-18 - [c211]Amir Masoud Gharehbaghi, Masahiro Fujita:
Transaction-based post-silicon debug of many-core System-on-Chips. ISQED 2012: 702-708 - [c210]Samaneh Ghandali, Bijan Alizadeh, Zainalabedin Navabi, Masahiro Fujita:
Polynomial datapath synthesis and optimization based on vanishing polynomial over Z2m and algebraic techniques. MEMOCODE 2012: 65-74 - [c209]Masahiro Fujita:
Future direction of digital content: 20th anniversary keynote talk. ACM Multimedia 2012: 1-2 - [c208]Koji Nakamaru, Toru Matsuoka, Masahiro Fujita:
Distance aware ray tracing for curves. SIGGRAPH Posters 2012: 103 - [c207]Mohammed Shayan, Virendra Singh, Adit D. Singh, Masahiro Fujita:
SEU Tolerant Robust Latch Design. VDAT 2012: 223-232 - [c206]Takeshi Matsumoto, Shohei Ono, Masahiro Fujita:
An efficient method to localize and correct bugs in high-level designs using counterexamples and potential dependence. VLSI-SoC 2012: 291-294 - [i2]Görschwin Fey, Masahiro Fujita, Natasa Miskov-Zivanov, Kaushik Roy, Matteo Sonza Reorda:
Verifying Reliability (Dagstuhl Seminar 12341). Dagstuhl Reports 2(8): 57-73 (2012) - 2011
- [j70]Tasuku Nishihara, Takeshi Matsumoto, Masahiro Fujita:
Multi-Level Bounded Model Checking with Symbolic Counterexamples. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 94-A(2): 696-705 (2011) - [j69]Yeonbok Lee, Takeshi Matsumoto, Masahiro Fujita:
An Automatic Method of Mapping I/O Sequences of Chip Execution onto High-level Design for Post-Silicon Debugging. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 94-A(7): 1519-1529 (2011) - [j68]Hiroaki Yoshida, Masahiro Fujita:
Performance-Constrained Transistor Sizing for Different Cell Count Minimization. Inf. Media Technol. 6(1): 1-11 (2011) - [j67]Hiroaki Yoshida, Masahiro Fujita:
Exact Minimum Factoring of Incompletely Specified Logic Functions via Quantified Boolean Satisfiability. Inf. Media Technol. 6(2): 286-295 (2011) - [j66]Hiroaki Yoshida, Masahiro Fujita:
Exact Minimum Factoring of Incompletely Specified Logic Functions via Quantified Boolean Satisfiability. IPSJ Trans. Syst. LSI Des. Methodol. 4: 70-79 (2011) - [j65]Ratna Krishnamoorthy, Saptarsi Das, Keshavan Varadarajan, Mythri Alle, Masahiro Fujita, Soumitra Kumar Nandy, Ranjani Narayan:
Data Flow Graph Partitioning Algorithms and Their Evaluations for Optimal Spatio-temporal Computation on a Coarse Grain Reconfigurable Architecture. IPSJ Trans. Syst. LSI Des. Methodol. 4: 193-209 (2011) - [j64]Paolo Zanotti-Fregonara, Sami S. Zoghbi, Jeih-San Liow, Elise Luong, Ronald Boellaard, Robert L. Gladding, Victor W. Pike, Robert B. Innis, Masahiro Fujita:
Kinetic analysis in human brain of [11C](R)-rolipram, a positron emission tomographic radioligand to image phosphodiesterase 4: A retest study and use of an image-derived input function. NeuroImage 54(3): 1903-1909 (2011) - [c205]Masahiro Fujita:
Accelerating Tsunami simulation with FPGA and GPU through automatic compilation. ACWR 2011: 79 - [c204]Ratna Krishnamoorthy, Keshavan Varadarajan, Masahiro Fujita, Mythri Alle, S. K. Nandy, Ranjani Narayan:
Dataflow Graph Partitioning for Optimal Spatio-Temporal Computation on a Coarse Grain Reconfigurable Architecture. ARC 2011: 125-132 - [c203]Masahiro Fujita:
Utilizing high level design information to speed up post-silicon debugging. ASP-DAC 2011: 301-305 - [c202]Yeonbok Lee, Takeshi Matsumoto, Masahiro Fujita:
On-chip dynamic signal sequence slicing for efficient post-silicon debugging. ASP-DAC 2011: 719-724 - [c201]Masahiro Fujita:
High Level Verification and Its Use at Pos-Silicon Debugging and Patching. Asian Test Symposium 2011: 464-469 - [c200]Masahiro Fujita:
Synthesizing, Verifying, and Debugging SoC with FSM-Based Specification of On-Chip Communication Protocols. ATVA 2011: 43-50 - [c199]Hiroaki Yoshida, Masahiro Fujita:
An energy-efficient patchable accelerator for post-silicon engineering changes. CODES+ISSS 2011: 13-20 - [c198]Viacheslav Izosimov, Michele Lora, Graziano Pravadelli, Franco Fummi, Zebo Peng, Giuseppe Di Guglielmo, Masahiro Fujita:
Optimization of Assertion Placement in Time-Constrained Embedded Systems. ETS 2011: 171-176 - [c197]Ratna Krishnamoorthy, Masahiro Fujita, Keshavan Varadarajan, S. K. Nandy:
Interconnect-topology independent mapping algorithm for a Coarse Grained Reconfigurable Architecture. FPT 2011: 1-5 - [c196]Bijan Alizadeh, Masahiro Fujita:
Modular equivalence verification of polynomial datapaths with multiple word-length operands. HLDVT 2011: 9-16 - [c195]Amir Masoud Gharehbaghi, Masahiro Fujita:
Formal verification guided automatic design error diagnosis and correction of complex processors. HLDVT 2011: 121-127 - [c194]Giuseppe Di Guglielmo, Masahiro Fujita, Luigi Di Guglielmo, Franco Fummi, Graziano Pravadelli, Cristina Marconcini, Andreas Foltinek:
Model-driven design and validation of embedded software. AST 2011: 98-104 - [c193]Hideo Tanida, Masahiro Fujita, Mukul R. Prasad, Sreeranga P. Rajan:
Client-tier Validation of Dynamic Web Applications. ICSOFT (2) 2011: 86-95 - [c192]Hideo Tanida, Mukul R. Prasad, Sreeranga P. Rajan, Masahiro Fujita:
Automated System Testing of Dynamic Web Applications. ICSOFT (Selected Papers) 2011: 181-196 - [c191]Bijan Alizadeh, Masahiro Fujita:
Early case splitting and false path detection to improve high level ATPG techniques. ISCAS 2011: 1463-1466 - [c190]Amir Masoud Gharehbaghi, Masahiro Fujita:
Global transaction ordering in Network-on-Chips for post-silicon validation. ISQED 2011: 284-289 - [c189]Bijan Alizadeh, Masahiro Fujita:
Debugging and optimizing high performance superscalar out-of-order processors using formal verification techniques. ISQED 2011: 297-302 - [c188]Sudipta Sarkar, Anubhav Adak, Virendra Singh, Kewal K. Saluja, Masahiro Fujita:
SEU tolerant SRAM cell. ISQED 2011: 597-602 - [c187]Giuseppe Di Guglielmo, Masahiro Fujita, Franco Fummi, Graziano Pravadelli, Stefano Soffia:
EFSM-based model-driven approach to concolic testing of system-level design. MEMOCODE 2011: 201-209 - [c186]Virendra Singh, Masahiro Fujita:
Tutorial: "Post silicon debug of SOC designs". SoCC 2011: 18 - 2010
- [j63]Kenshu Seto, Masahiro Fujita:
Custom Instruction Generation for Configurable Processors with Limited Numbers of Operands. Inf. Media Technol. 5(2): 376-387 (2010) - [j62]Kenshu Seto, Masahiro Fujita:
Custom Instruction Generation for Configurable Processors with Limited Numbers of Operands. IPSJ Trans. Syst. LSI Des. Methodol. 3: 57-68 (2010) - [j61]Takeshi Matsumoto, Tasuku Nishihara, Masahiro Fujita:
Performance Estimation with Automatic False-Path Detection for System-Level Designs. IPSJ Trans. Syst. LSI Des. Methodol. 3: 69-80 (2010) - [j60]Hiroaki Yoshida, Masahiro Fujita:
Performance-Constrained Transistor Sizing for Different Cell Count Minimization. J. Inf. Process. 18: 252-262 (2010) - [j59]William C. Kreisl, Masahiro Fujita, Yota Fujimura, Nobuyo Kimura, Kimberly J. Jenko, Pavitra Kannan, Jinsoo Hong, Cheryl L. Morse, Sami S. Zoghbi, Robert L. Gladding, Steven Jacobson, Unsong Oh, Victor W. Pike, Robert B. Innis:
Comparison of [11C]-(R)-PK 11195 and [11C]PBR28, two radioligands for translocator protein (18 kDa) in human and monkey: Implications for positron emission tomographic imaging of this inflammation biomarker. NeuroImage 49(4): 2924-2932 (2010) - [j58]Paolo Zanotti-Fregonara, Sami S. Zoghbi, Jeih-San Liow, Jinsoo Hong, Ronald Boellaard, Victor W. Pike, Robert B. Innis, Masahiro Fujita:
Category: Methodology: Quantification and test-retest study of 11C-(R)-rolipram, a PET tracer of the cAMP cascade, using an arterial input function and an image-derived input function. NeuroImage 52(Supplement-1): S161 (2010) - [j57]Paolo Zanotti-Fregonara, Jeih-San Liow, Masahiro Fujita, Sami S. Zoghbi, Claude Comtat, Elise Luong, Ronald Boellaard, Victor W. Pike, Robert B. Innis:
Image-derived input function for brain imaging using the high-resolution research tomograph. NeuroImage 52(Supplement-1): S222 (2010) - [j56]Masahiro Fujita, Alan G. Mallinger, Carlos A. Zarate Jr., Leah P. Dickstein, Sami S. Zoghbi, Victor W. Pike, Yi Zhang, Robert B. Innis, Wayne C. Drevets:
Changes of brain phosphodiesterase 4 in major depression. NeuroImage 52(Supplement-1): S51 (2010) - [j55]Bijan Alizadeh, Mohammad Mirzaei, Masahiro Fujita:
Coverage Driven High-Level Test Generation Using a Polynomial Model of Sequential Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(5): 737-748 (2010) - [j54]Bijan Alizadeh, Masahiro Fujita:
Modular Datapath Optimization and Verification Based on Modular-HED. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(9): 1422-1435 (2010) - [c185]Bijan Alizadeh, Amir Masoud Gharehbaghi, Masahiro Fujita:
Pipelined Microprocessors Optimization and Debugging. ARC 2010: 435-444 - [c184]Bijan Alizadeh, Masahiro Fujita:
Guided gate-level ATPG for sequential circuits using a high-level test generation approach. ASP-DAC 2010: 425-430 - [c183]Ratna Krishnamoorthy, Keshavan Varadarajan, Ganesh Garga, Mythri Alle, S. K. Nandy, Ranjani Narayan, Masahiro Fujita:
Towards minimizing execution delays on dynamically reconfigurable processors: a case study on REDEFINE. CASES 2010: 77-86 - [c182]Amir Masoud Gharehbaghi, Bijan Alizadeh, Masahiro Fujita:
Aggressive overclocking support using a novel timing error recovery technique on FPGAs (abstract only). FPGA 2010: 288 - [c181]Bijan Alizadeh, Masahiro Fujita:
A debugging method for repairing post-silicon bugs of high performance processors in the fields. FPT 2010: 328-331 - [c180]Sudipta Sarkar, Anubhav Adak, Virendra Singh, Kewal K. Saluja, Masahiro Fujita:
SEU tolerant SRAM for FPGA applications. FPT 2010: 491-494 - [c179]Finn Haedicke, Bijan Alizadeh, Görschwin Fey, Masahiro Fujita, Rolf Drechsler:
Polynomial datapath optimization using constraint solving and formal modelling. ICCAD 2010: 756-761 - [c178]Yeonbok Lee, Takeshi Matsumoto, Masahiro Fujita:
Generation of I/O sequences for a high-level design from those in post-silicon for efficient post-silicon debugging. ICCD 2010: 402-408 - [c177]Masahiro Fujita, Hideo Tanida, Fei Gao, Tasuku Nishihara, Takeshi Matsumoto:
Synthesis and formal verification of on-chip protocol transducers through decomposed specification. ISQED 2010: 515-523 - [c176]Guillermo Lopez, Tomoki Tanemura, Ryo Sato, Takahiro Saeki, Yoshikazu Hirai, Koji Sugano, Toshiyuki Tsuchiya, Osamu Tabata, Masahiro Fujita, Mizuo Maeda:
DNA-grafted-polymer mediated self-assembly of micro components. NEMS 2010: 245-249
2000 – 2009
- 2009
- [j53]Masahiro Fujita:
Intelligence Dynamics: a concept and preliminary experiments for open-ended learning agents. Auton. Agents Multi Agent Syst. 19(3): 248-271 (2009) - [j52]Anmol Mathur, Masahiro Fujita, Edmund M. Clarke, Pascal Urard:
Functional Equivalence Verification Tools in High-Level Synthesis Flows. IEEE Des. Test Comput. 26(4): 88-95 (2009) - [j51]Tasuku Nishihara, Takeshi Matsumoto, Masahiro Fujita:
Word-Level Equivalence Checking in Bit-Level Accuracy by Synthesizing Designs onto Identical Datapath. IEICE Trans. Inf. Syst. 92-D(5): 972-984 (2009) - [j50]Bijan Alizadeh, Masahiro Fujita:
A Unified Framework for Equivalence Verification of Datapath Oriented Applications. IEICE Trans. Inf. Syst. 92-D(5): 985-994 (2009) - [j49]Shanghua Gao, Hiroaki Yoshida, Kenshu Seto, Satoshi Komatsu, Masahiro Fujita:
Interconnect-Aware Pipeline Synthesis for Array-Based Architectures. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(6): 1464-1475 (2009) - [j48]Masahiro Fujita:
Trends in Formal Verification Techniques for C-based Hardware Designs. Inf. Media Technol. 4(2): 149-164 (2009) - [j47]Masahiro Fujita:
Trends in Formal Verification Techniques for C-based Hardware Designs. IPSJ Trans. Syst. LSI Des. Methodol. 2: 2-17 (2009) - [j46]Omid Sarbishei, Mahmoud Tabandeh, Bijan Alizadeh, Masahiro Fujita:
A Formal Approach for Debugging Arithmetic Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(5): 742-754 (2009) - [c175]Yeonbok Lee, Tasuku Nishihara, Takeshi Matsumoto, Masahiro Fujita:
A Post-Silicon Debug Support Using High-Level Design Description. Asian Test Symposium 2009: 137-142 - [c174]Masahiro Fujita, Yoshihisa Kojima, Amir Masoud Gharehbaghi:
Debugging from high level down to gate level. DAC 2009: 627-630 - [c173]Omid Sarbishei, Bijan Alizadeh, Masahiro Fujita:
Polynomial datapath optimization using partitioning and compensation heuristics. DAC 2009: 931-936 - [c172]Bijan Alizadeh, Masahiro Fujita:
Modular arithmetic decision procedure with auto-correction mechanism. HLDVT 2009: 138-145 - [c171]Bijan Alizadeh, Masahiro Fujita:
Improved heuristics for finite word-length polynomial datapath optimization. ICCAD 2009: 739-744 - [c170]Amir Masoud Gharehbaghi, Masahiro Fujita:
Transaction-based debugging of system-on-chips with patterns. ICCD 2009: 186-192 - [c169]Hiroaki Yoshida, Masahiro Fujita:
Improving the accuracy of rule-based equivalence checking of system-level design descriptions by identifying potential internal equivalences. ISQED 2009: 366-370 - [c168]Omid Sarbishei, Mahmoud Tabandeh, Bijan Alizadeh, Masahiro Fujita:
High-level optimization of integer multipliers over a finite bit-width with verification capabilities. MEMOCODE 2009: 56-65 - [e1]Bernd Becker, V. Bertacoo, Rolf Drechsler, Masahiro Fujita:
Algorithms and Applications for Next Generation SAT Solvers, 08.11. - 13.11.2009. Dagstuhl Seminar Proceedings 09461, Schloss Dagstuhl - Leibniz-Zentrum für Informatik, Germany 2009 [contents] - [i1]Bernd Becker, Valeria Bertacco, Rolf Drechsler, Masahiro Fujita:
09461 Abstracts Collection - Algorithms and Applications for Next Generation SAT Solvers. Algorithms and Applications for Next Generation SAT Solvers 2009 - 2008
- [b1]Masahiro Fujita, Indradeep Ghosh, Mukul R. Prasad:
Verification Techniques for System-Level Design. The Morgan Kaufmann series in systems on silicon, Morgan Kaufmann 2008, ISBN 978-0-12-370616-4, pp. I-VIII, 1-240 - [j45]Jens-Steffen Gutmann, Masaki Fukuchi, Masahiro Fujita:
3D Perception and Environment Map Generation for Humanoid Robot Navigation. Int. J. Robotics Res. 27(10): 1117-1134 (2008) - [j44]Masahiro Fujita, Kenshu Seto, Thanyapat Sakunkonchak:
Dependence Graph Based Verification and Synthesis of Hardware/Software Co-Designs with SAT Related Formulation. J. Satisf. Boolean Model. Comput. 5(1-4): 57-82 (2008) - [j43]Masao Imaizumi, Emmanuelle Briard, Sami S. Zoghbi, Jonathan P. Gourley, Jinsoo Hong, Yota Fujimura, Victor W. Pike, Robert B. Innis, Masahiro Fujita:
Brain and whole-body imaging in nonhuman primates of [11C]PBR28, a promising PET radioligand for peripheral benzodiazepine receptors. NeuroImage 39(3): 1289-1298 (2008) - [j42]Masahiro Fujita, Masao Imaizumi, Sami S. Zoghbi, Yota Fujimura, Amanda G. Farris, Tetsuya Suhara, Jinsoo Hong, Victor W. Pike, Robert B. Innis:
Kinetic analysis in healthy humans of a novel positron emission tomography radioligand to image the peripheral benzodiazepine receptor, a potential biomarker for inflammation. NeuroImage 40(1): 43-52 (2008) - [c167]Görschwin Fey, Satoshi Komatsu, Yasuo Furukawa, Masahiro Fujita:
Targeting Leakage Constraints during ATPG. ATS 2008: 225-230 - [c166]Yoshihisa Kojima, Tasuku Nishihara, Takeshi Matsumoto, Masahiro Fujita:
An Interactive Verification and Debugging Environment by Concrete/Symbolic Simulations for System-Level Designs. ATS 2008: 315-320 - [c165]Bijan Alizadeh, Masahiro Fujita:
Sequential Equivalence Checking Using a Hybrid Boolean-Word Level Decision Diagram. CSICC 2008: 697-704 - [c164]Hiroaki Yoshida, Masahiro Fujita:
Performance-Constrained Different Cell Count Minimization for Continuously-Sized Circuits. DATE 2008: 1099-1102 - [c163]Tasuku Nishihara, Takeshi Matsumoto, Masahiro Fujita:
Multi-level Bounded Model Checking to detect bugs beyond the bound. HLDVT 2008: 49-55 - [c162]Taro Takahashi, Toshimitsu Tsuboi, Takeo Kishida, Yasunori Kawanami, Satoru Shimizu, Masatsugu Iribe, Tetsuharu Fukushima, Masahiro Fujita:
Adaptive grasping by multi fingered hand with tactile sensor based on robust force and position control. ICRA 2008: 264-271 - [c161]Masahiro Fujita, Takeshi Matsumoto, Hiroaki Yoshida:
A HW/SW Co-Reuse Methodology Based on Design Refinement Templates in UML Diagrams. ICSOFT (SE/MUSE/GSDCA) 2008: 240-245 - [c160]Ken'ichiro Nagasaka, Atsushi Miyamoto, Masakuni Nagano, Hirokazu Shirado, Tetsuharu Fukushima, Masahiro Fujita:
Motion control of a virtual humanoid that can perform real physical interactions with a human. IROS 2008: 2303-2310 - [c159]Omid Sarbishei, Bijan Alizadeh, Masahiro Fujita:
Arithmetic Circuits Verification without Looking for Internal Equivalences. MEMOCODE 2008: 7-16 - [c158]Subash Shankar, Masahiro Fujita:
Rule-Based Approaches for Equivalence Checking of SpecC Programs. MEMOCODE 2008: 39-48 - [c157]Kenshu Seto, Masahiro Fujita:
Custom Instruction Generation with High-Level Synthesis. SASP 2008: 14-19 - 2007
- [j41]Masahiro Fujita, Yukio Yamaguchi:
Multiscale simulation method for self-organization of nanoparticles in dense suspension. J. Comput. Phys. 223(1): 108-120 (2007) - [j40]Shunsuke Sasaki, Tasuku Nishihara, Daisuke Ando, Masahiro Fujita:
Hardware/Software Co-design and Verification Methodology from System Level Based on System Dependence Graph. J. Univers. Comput. Sci. 13(13): 1972-2001 (2007) - [j39]Masahiro Fujita, Sami S. Zoghbi, Matthew S. Crescenzo, Jinsoo Hong, John L. Musachio, Jian-Qiang Lu, Jeih-San Liow, Nicholas Seneca, Dnyanesh N. Tipre, Vanessa L. Cropley, Masao Imaizumi, Antony D. Gee, Jürgen Seidel, Michael V. Green, Victor W. Pike, Robert B. Innis:
Corrigendum to "Quantification of brain phosphodiesterase 4 in rat with (R)-[11C]rolipram-PET" [NeuroImage 26 (2005) 1201-1210]. NeuroImage 36(4): 1399 (2007) - [c156]Shigeru Watanabe, Kenshu Seto, Yuji Ishikawa, Satoshi Komatsu, Masahiro Fujita:
Protocol Transducer Synthesis using Divide and Conquer approach. ASP-DAC 2007: 280-285 - [c155]Bijan Alizadeh, Masahiro Fujita:
Automatic Merge-Point Detection for Sequential Equivalence Checking of System-Level and RTL Descriptions. ATVA 2007: 129-144 - [c154]Thanyapat Sakunkonchak, Satoshi Komatsu, Masahiro Fujita:
Using Counterexample Analysis to Minimize the Number of Predicates for Predicate Abstraction. ATVA 2007: 553-563 - [c153]Takeshi Matsumoto, Daisuke Ando, Tasuku Nishihara, Masahiro Fujita:
Development and Verification of a Collaborative Printing Environment. C5 2007: 99-108 - [c152]Bijan Alizadeh, Masahiro Fujita:
A novel formal approach to generate high-level test vectors without ILP and SAT solvers. HLDVT 2007: 97-104 - [c151]Shanghua Gao, Kenshu Seto, Satoshi Komatsu, Masahiro Fujita:
Interconnect-aware Pipeline Synthesis for Array based Reconfigurable Architectures. IESS 2007: 121-134 - [c150]Makoto Aso, Masahiro Fujita, Keitaro Niki:
Lateral State Prediction for Automated Steering using Reliability-Weighted Measurements from Multiple Sensors. ITSC 2007: 461-466 - [c149]Satoshi Komatsu, Kazuyoshi Takagi, Masahiro Fujita, Kunihiro Asada:
VLSI CAD Education and Exercise Course with Public Domain Tools. MSE 2007: 111-112 - 2006
- [j38]Yu Liu, Satoshi Komatsu, Masahiro Fujita:
Synchronization Mechanism for Timed/Untimed Mixed-Signal System Level Design Environment. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(4): 1018-1026 (2006) - [j37]Thanyapat Sakunkonchak, Satoshi Komatsu, Masahiro Fujita:
Synchronization Verification in System-Level Design with ILP Solvers. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(12): 3387-3396 (2006) - [j36]Yu Liu, Satoshi Komatsu, Masahiro Fujita:
The AMS Extension to System Level Design Language - SpecC. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(12): 3397-3407 (2006) - [j35]David W. Currie, Xiushan Feng, Masahiro Fujita, Alan J. Hu, Mark Kwan, Sreeranga P. Rajan:
Embedded Software Verification Using Symbolic Execution and Uninterpreted Functions. Int. J. Parallel Program. 34(1): 61-91 (2006) - [c148]Ken Matsui, Masahiro Fujita:
Object-oriented analysis and specification for HW/SW co-design with UML diagrams. ACST 2006: 38-43 - [c147]Masahiro Fujita, Tasuku Nishihara, Daisuke Ando:
System LSI distributed collaborative design environment for both designers and CAD developers/engineers. C5 2006: 175-183 - [c146]Shota Watanabe, Yuji Ishikawa, Kenshu Seto, Satoshi Komatsu, Masahiro Fujita:
Dynamically reconfigurable protocol transducer. FPT 2006: 341-344 - [c145]Tasuku Nishihara, Takeshi Matsumoto, Masahiro Fujita:
Equivalence Checking with Rule-Based Equivalence Propagation and High-Level Synthesis. HLDVT 2006: 162-169 - [c144]Satoshi Komatsu, Masahiro Fujita:
An optimization of bus interconnects pitch for low-power and reliable bus encoding scheme. ISCAS 2006 - [c143]Takeshi Matsumoto, Hiroshi Saito, Masahiro Fujita:
Equivalence Checking of C Programs by Locally Performing Symbolic Simulation on Dependence Graphs. ISQED 2006: 370-375 - [c142]Masahiro Fujita, Subash Shankar, Sasaki Shunsuke:
Equivalence checking: a rule-based approach. MEMOCODE 2006: 197 - [c141]Anmol Mathur, Masahiro Fujita, M. Balakrishnan, Raj S. Mitra:
Sequential Equivalence Checking. VLSI Design 2006: 18-19 - 2005
- [j34]Satoshi Komatsu, Masahiro Fujita:
Low Power and Fault Tolerant Encoding Methods for On-Chip Data Transfer in Practical Applications. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(12): 3282-3289 (2005) - [j33]Takeshi Matsumoto, Hiroshi Saito, Masahiro Fujita:
An Equivalence Checking Method for C Descriptions Based on Symbolic Simulation with Textual Differences. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(12): 3315-3323 (2005) - [j32]Masahiro Fujita, Sami S. Zoghbi, Matthew S. Crescenzo, Jinsoo Hong, John L. Musachio, Jian-Qiang Lu, Jeih-San Liow, Nicholas Seneca, Dnyanesh N. Tipre, Vanessa L. Cropley, Masao Imaizumi, Antony D. Gee, Jürgen Seidel, Michael V. Green, Victor W. Pike, Robert B. Innis:
Quantification of brain phosphodiesterase 4 in rat with (R)-[11C]Rolipram-PET. NeuroImage 26(4): 1201-1210 (2005) - [j31]Masahiro Fujita:
Equivalence checking between behavioral and RTL descriptions with virtual controllers and datapaths. ACM Trans. Design Autom. Electr. Syst. 10(4): 610-626 (2005) - [j30]Gregory S. Hornby, Seiichi Takamura, Takashi Yamamoto, Masahiro Fujita:
Autonomous evolution of dynamic gaits with two quadruped robots. IEEE Trans. Robotics 21(3): 402-410 (2005) - [c140]Masahiro Fujita:
Behavior-RTL Equivalence Checking Based on Data Transfer Analysis with Virtual Controllers and Datapaths. CHARME 2005: 340-344 - [c139]Yosuke Bando, Takahiro Saito, Masahiro Fujita:
Hexagonal storage scheme for interleaved frame buffers and textures. Graphics Hardware 2005: 33-40 - [c138]Yu Liu, Satoshi Komatsu, Masahiro Fujita:
AMS Extensions for Timed/Untimed System-Level Design Language. FDL 2005: 77-81 - [c137]Shanghua Gao, Kenshu Seto, Satoshi Komatsu, Masahiro Fujita:
Pipeline Scheduling for Array Based Reconfigurable Architectures Considering Interconnect Delays. FPT 2005: 137-144 - [c136]Yu Liu, Thanyapat Sakunkonchak, Satoshi Komatsu, Masahiro Fujita:
System level design language extensions for timed/untimed digital-analog combined system design. ACM Great Lakes Symposium on VLSI 2005: 130-133 - [c135]Jens-Steffen Gutmann, Masaki Fukuchi, Masahiro Fujita:
A modular architecture for humanoid robot navigation. Humanoids 2005: 26-31 - [c134]Jens-Steffen Gutmann, Masaki Fukuchi, Masahiro Fujita:
A Floor and Obstacle Height Map for 3D Navigation of a Humanoid Robot. ICRA 2005: 1066-1071 - [c133]Jens-Steffen Gutmann, Masaki Fukuchi, Masahiro Fujita:
Real-Time Path Planning for Humanoid Robot Navigation. IJCAI 2005: 1232-1237 - [c132]Masahiro Fujita, Shunsuke Sasaki, Ken Matsui:
Object-oriented analysis and design of hardware/software co-designs with dependence analysis for design reuse. IRI 2005: 318-325 - [c131]Thanyapat Sakunkonchak, Satoshi Komatsu, Masahiro Fujita:
Synchronization verification in system-level design with ILP solvers. MEMOCODE 2005: 121-130 - [c130]Masahiro Fujita:
Extended abstract: a formal design approach from software oriented UML descriptions to hardware oriented RTL. MEMOCODE 2005: 241-242 - [c129]Shunsuke Sasaki, Tasuku Nishihara, Masahiro Fujita:
Slicing-based Hardware/Software Co-design Methodology From Functional Specifications. FSEN 2005: 265-280 - 2004
- [j29]Masahiro Fujita:
On activating human communications with pet-type robot AIBO. Proc. IEEE 92(11): 1804-1813 (2004) - [c128]Masahiro Fujita, Takashi Kanai:
Precomputed Radiance Transfer with Spatially-Varying Lighting Effects. CGIV 2004: 101-108 - [c127]Masahiro Fujita:
On equivalence checking between behavioral and RTL descriptions. HLDVT 2004: 179-184 - [c126]Tsutomu Sawada, Tsuyoshi Takagi, Yukiko Hoshino, Masahiro Fujita:
Learning behavior selection through interaction based on emotionally grounded symbol concept. Humanoids 2004: 450-469 - [c125]Yukiko Hoshino, Tsuyoshi Takagi, Ugo Di Profio, Masahiro Fujita:
Behavior Description and Control using Behavior Module for Personal Robot. ICRA 2004: 4165-4171 - [c124]Jens-Steffen Gutmann, Masaki Fukuchi, Masahiro Fujita:
Stair climbing for humanoid robots using stereo vision. IROS 2004: 1407-1413 - [c123]Tsutomu Sawada, Tsuyoshi Takagi, Masahiro Fujita:
Behavior selection and motion modulation in emotionally grounded architecture for QRIO SDR-4XII. IROS 2004: 2514-2519 - [c122]Fumihide Tanaka, Kuniaki Noda, Tsutomu Sawada, Masahiro Fujita:
Associated Emotion and Its Expression in an Entertainment Robot QRIO. ICEC 2004: 499-504 - [c121]Indradeep Ghosh, Rajarshi Mukherjee, Mukul R. Prasad, Masahiro Fujita:
High Level Design Validation: Current Practices and Future Directions. VLSI Design 2004: 9-11 - [c120]Masahiro Fujita:
Formal Verification of C Language Based VLSI Designs. VLSI Design 2004: 93- - 2003
- [j28]Minoru Asada, Oliver Obst, Daniel Polani, Brett Browning, Andrea Bonarini, Masahiro Fujita, Thomas Christaller, Tomoichi Takahashi, Satoshi Tadokoro, Elizabeth Sklar, Gal A. Kaminka:
An Overview of RoboCup-2002 Fukuoka/Busan. AI Mag. 24(2): 21-40 (2003) - [j27]Satoshi Komatsu, Masahiro Fujita:
Irredundant Low Power Address Bus Encoding Techniques Based on Adaptive Codebooks. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(12): 3001-3008 (2003) - [j26]Thanyapat Sakunkonchak, Satoshi Komatsu, Masahiro Fujita:
Verification of Synchronization in SpecC Description with the Use of Difference Decision Diagrams. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(12): 3192-3199 (2003) - [j25]Ronald C. Arkin, Masahiro Fujita, Tsuyoshi Takagi, Rika Hasegawa:
An ethological and emotional basis for human-robot interaction. Robotics Auton. Syst. 42(3-4): 191-201 (2003) - [c119]Satoshi Komatsu, Masahiro Fujita:
Irredundant address bus encoding techniques based on adaptive codebooks for low power. ASP-DAC 2003: 9-14 - [c118]Farzan Fallah, Indradeep Ghosh, Masahiro Fujita:
Event-driven observability enhanced coverage analysis of C programs for functional validation. ASP-DAC 2003: 123-128 - [c117]Hiroshi Saito, Hiroshi Nakamura, Masahiro Fujita, Takashi Nanya:
Logic optimization for asynchronous speed independent controllers using transduction method. ASP-DAC 2003: 197-202 - [c116]Rajesh K. Gupta, Shishpal Rawat, Sandeep K. Shukla, Brian Bailey, Daniel K. Beece, Masahiro Fujita, Carl Pixley, John O'Leary, Fabio Somenzi:
Formal verification - prove it or pitch it. DAC 2003: 710-711 - [c115]Edmund M. Clarke, Masahiro Fujita, David P. Gluch:
Model Checking for Dependable Software-Intensive Systems. DSN 2003: 764 - [c114]Masahiro Fujita, Satoshi Komatsu, Hiroshi Saito, Kenshu Seto, Thanyapat Sakunkonchak, Yoshihisa Kojima:
Field Modifiable Architecture with FPGAs and its Design/Verification/Debugging Methodologies. HICSS 2003: 279 - [c113]Yoshihiro Kuroki, Masahiro Fujita, Tatsuzo Ishida, Ken'ichiro Nagasaka, Jin'ichi Yamaguchi:
A small biped entertainment robot exploring attractive applications. ICRA 2003: 471-476 - [c112]Masahiro Fujita, Yoshihiro Kuroki, Tatsuzo Ishida, Toshi T. Doi:
Autonomous behavior control architecture of entertainment humanoid robot SDR-4X. IROS 2003: 960-967 - [c111]Masahiro Fujita, Kohtaro Sabe, Yoshihiro Kuroki, Tatsuzo Ishida, Toshi T. Doi:
SDR-4X II: A Small Humanoid as an Entertainer in Home Environment. ISRR 2003: 355-364 - [c110]Hiroshi Saito, Kenshu Seto, Yoshihisa Kojima, Satoshi Komatsu, Masahiro Fujita:
Engineering Changes in Field Modifiable Architectures. MEMOCODE 2003: 87-94 - [c109]Tohru Ishihara, Satoshi Komatsu, Makoto Ikeda, Masahiro Fujita, Kunihiro Asada:
Comparative Study On Verilog-Based And C-Based Hardware Design Education. MSE 2003: 41-42 - [c108]Tetsuro Ogi, Toshio Yamada, Michitaka Hirose, Masahiro Fujita, Kazuto Kuzuu:
High Presence Remote Presentation in the Shared Immersive Virtual World. VR 2003: 289-290 - 2002
- [j24]Rajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Jacob A. Abraham, Donald S. Fussell, Masahiro Fujita:
Efficient Combinational Verification Using Overlapping Local BDDs and a Hash Table. Formal Methods Syst. Des. 21(1): 95-101 (2002) - [j23]Yoshihiro Kuroki, Tatsuzo Ishida, Jin'ichi Yamaguchi, Masahiro Fujita, Toshi T. Doi:
A Small Biped Entertainment Robot. J. Robotics Mechatronics 14(1): 6-12 (2002) - [j22]Pedro U. Lima, Tucker R. Balch, Masahiro Fujita, Raúl Rojas, Manuela M. Veloso, Holly A. Yanco:
RoboCup 2001. IEEE Robotics Autom. Mag. 9(2): 20-30 (2002) - [j21]Hans-Dieter Burkhard, Dominique Duhaut, Masahiro Fujita, Pedro U. Lima, Robin R. Murphy, Raúl Rojas:
The road to RoboCup 2050. IEEE Robotics Autom. Mag. 9(2): 31-38 (2002) - [j20]Edmund M. Clarke, Masahiro Fujita, Sreeranga P. Rajan, Thomas W. Reps, Subash Shankar, Tim Teitelbaum:
Program slicing for VHDL. Int. J. Softw. Tools Technol. Transf. 4(1): 125-137 (2002) - [c107]Masahiro Fujita, Takashi Kanai:
Hardware-Assisted Relief Texture Mapping. Eurographics (Short Presentations) 2002 - [c106]Thanyapat Sakunkonchak, Masahiro Fujita:
Verification of Event-Based Synchronization of SpecC Description Using Difference Decision Diagrams. FORTE 2002: 369 - [c105]Masao Kubo, Masahiro Fujita:
Debug methodology for arithmetic circuits on FPGAs. FPT 2002: 236-242 - [c104]Satoshi Komatsu, Yoshihisa Kojima, Hiroshi Saito, Kenshu Seto, Masahiro Fujita:
Field modifiable architecture with FPGAs and its design methodology. FPT 2002: 382-385 - [c103]Hiroshi Saito, Takaya Ogawa, Thanyapat Sakunkonchak, Masahiro Fujita, Takashi Nanya:
An equivalence checking methodology for hardware oriented C-based specifications. HLDVT 2002: 139-144 - [c102]Yoshihisa Kojima, Hiroshi Saito, Kenshu Seto, Satoshi Komatsu, Masahiro Fujita:
Field Modifiable Architecture and its Design Methodology: System Design Without Logic Synthesis. IWLS 2002: 103-108 - [c101]Hiroshi Saito, Hiroshi Nakamura, Masahiro Fujita, Takashi Nanya:
Logic Optimization for Asynchronous SI Controllers using Transduction Method. IWLS 2002: 245-250 - [c100]Hiroshi Nakamura, Takanori Arai, Masahiro Fujita:
Formal Verification of a Pipelined Processor with New Memory. PRDC 2002: 321-324 - [c99]Masahiro Fujita:
Sony Four Legged Robot League at RoboCup 2002. RoboCup 2002: 469-476 - [c98]Hiroaki Yoshida, Motohiro Sera, Masao Kubo, Masahiro Fujita:
Simultaneous Circuit Transformation and Routing. ASP-DAC/VLSI Design 2002: 479-483 - 2001
- [j19]Masahiro Fujita:
AIBO: Toward the Era of Digital Creatures. Int. J. Robotics Res. 20(10): 781-794 (2001) - [j18]Jawahar Jain, Ingo Wegener, Masahiro Fujita:
A Note on Complexity of OBDD Composition and Efficiency of Partitioned-OBDDs over OBDDs. IEEE Trans. Computers 50(11): 1289-1290 (2001) - [j17]Indradeep Ghosh, Masahiro Fujita:
Automatic test pattern generation for functional register-transferlevel circuits using assignment decision diagrams. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(3): 402-415 (2001) - [c97]Masahiro Fujita, Gabriel Costa, Rika Hasegawa, Tsuyoshi Takagi, Jun Yokono, Hideki Shimomura:
Architecture and preliminary experimental results for emotionally grounded symbol acquisition. Agents 2001: 35-36 - [c96]Ronald C. Arkin, Masahiro Fujita, Tsuyoshi Takagi, Rika Hasegawa:
Ethological Modeling and Architecture for an Entertainment Robot. ICRA 2001: 453-458 - [c95]Tatsuzo Ishida, Yoshihiro Kuroki, Jin'ichi Yamaguchi, Masahiro Fujita, Toshi T. Doi:
Motion entertainment by a small humanoid robot based on OPEN-R. IROS 2001: 1079-1086 - [c94]Masahiro Fujita, Hiroshi Nakamura:
The standard SpecC language. ISSS 2001: 81-86 - [c93]Wolfgang Rosenstiel, Brian Bailey, Masahiro Fujita, Guang R. Gao, Rajesh K. Gupta, Preeti Ranjan Panda:
New Design Paradigms: What Needs to be Standardized?. ISSS 2001: 94 - [c92]Takashi Michikawa, Takashi Kanai, Masahiro Fujita, Hiroaki Chiyokura:
Multiresolution Interpolation Meshes. PG 2001: 60-69 - 2000
- [j16]Masahiro Fujita, Manuela M. Veloso, William T. B. Uther, Minoru Asada, Hiroaki Kitano, Vincent Hugel, Patrick Bonnin, Jean-Christophe Bouramoué, Pierre Blazevic:
Vision, Strategy, and Localization Using the Sony Robots at RoboCup-98. AI Mag. 21(1): 47-56 (2000) - [c91]Rajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Masahiro Fujita:
Automatic partitioning for efficient combinatorial verification. ASP-DAC 2000: 67-72 - [c90]Indradeep Ghosh, Masahiro Fujita:
Automatic test pattern generation for functional RTL circuits using assignment decision diagrams. DAC 2000: 43-48 - [c89]Yuan Lu, Jawahar Jain, Edmund M. Clarke, Masahiro Fujita:
Efficient variable ordering using aBDD based sampling. DAC 2000: 687-692 - [c88]Gregory Hornby, Seiichi Takamura, Osamu Hanagata, Masahiro Fujita, Jordan B. Pollack:
Evolution of Controllers from a High-Level Simulator to a High DOF Robot. ICES 2000: 80-89 - [c87]Masahiro Fujita:
Digital Creatures for Future Entertainment Robotics. ICRA 2000: 801-806 - [c86]Gregory Hornby, Seiichi Takamura, Jun Yokono, Osamu Hanagata, Takashi Yamamoto, Masahiro Fujita:
Evolving Robust Gaits with AIBO. ICRA 2000: 3040-3045 - [c85]Takashi Yamamoto, Masahiro Fujita:
A quadruped robot platform with basic software for RoboCup-99 legged robot league. IROS 2000: 1026-1031 - [c84]Minoru Asada, Andreas Birk, Enrico Pagello, Masahiro Fujita, Itsuki Noda, Satoshi Tadokoro, Dominique Duhaut, Peter Stone, Manuela M. Veloso, Tucker R. Balch, Hiroaki Kitano, Brian Thomas:
Progress in RoboCup Soccer Research in 2000. ISER 2000: 363-372 - [c83]Peter Stone, Minoru Asada, Tucker R. Balch, Masahiro Fujita, Gerhard K. Kraetzschmar, Henrik Hautop Lund, Paul Scerri, Satoshi Tadokoro, Gordon F. Wyeth:
Overview of RoboCup-2000. RoboCup 2000: 1-28 - [c82]Vamsi Boppana, Indradeep Ghosh, Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita:
Hierarchical Error Diagnosis Targeting RTL Circuits. VLSI Design 2000: 436-441 - [c81]Ankur Jain, Vamsi Boppana, Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita, Michael S. Hsiao:
Testing, Verification, and Diagnosis in the Presence of Unknowns. VTS 2000: 263-270
1990 – 1999
- 1999
- [j15]Ashok Sudarsanam, Sharad Malik, Masahiro Fujita:
A Retargetable Compilation Methodology for Embedded Digital Signal Processors Using a Machine-Dependent Code Optimization Library. Des. Autom. Embed. Syst. 4(2-3): 187-206 (1999) - [j14]Masahiro Fujita, Hiroaki Kitano, Koji Kageyama:
A reconfigurable robot platform. Robotics Auton. Syst. 29(2-3): 119-132 (1999) - [j13]Rajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Masahiro Fujita, Jacob A. Abraham, Donald S. Fussell:
An efficient filter-based approach for combinational verification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(11): 1542-1557 (1999) - [c80]Vamsi Boppana, Sreeranga P. Rajan, Koichiro Takayama, Masahiro Fujita:
Model Checking Based on Sequential ATPG. CAV 1999: 418-430 - [c79]Edmund M. Clarke, Masahiro Fujita, Sreeranga P. Rajan, Thomas W. Reps, Subash Shankar, Tim Teitelbaum:
Program Slicing of Hardware Description Languages. CHARME 1999: 298-312 - [c78]Sreeranga P. Rajan, Masahiro Fujita, Ashok Sudarsanam, Sharad Malik:
Development of an optimizing compiler for a Fujitsu fixed-point digital signal processor. CODES 1999: 2-6 - [c77]Armin Biere, Alessandro Cimatti, Edmund M. Clarke, Masahiro Fujita, Yunshan Zhu:
Symbolic Model Checking Using SAT Procedures instead of BDDs. DAC 1999: 317-320 - [c76]Vamsi Boppana, Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita, Pradeep Bollineni:
Multiple Error Diagnosis Based on Xlists. DAC 1999: 660-665 - [c75]Rajeev Murgai, Masahiro Fujita:
On Reducing Transitions Through Data Modifications. DATE 1999: 82- - [c74]Rajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Masahiro Fujita, Jacob A. Abraham, Donald S. Fussell:
An Efficient Filter-Based Approach for Combinational Verification. DATE 1999: 132-137 - [c73]Rajeev Murgai, Fumiyasu Hirose, Masahiro Fujita:
Speeding Up Look-up-Table Driven Logic Simulation. VLSI 1999: 385-397 - [c72]Masahiro Fujita, Hiroaki Kitano, Toshitada Doi:
Syntactic-semantic analysis of reconfigurable robot. IROS 1999: 1567-1572 - [c71]Manuela M. Veloso, Hiroaki Kitano, Enrico Pagello, Gerhard K. Kraetzschmar, Peter Stone, Tucker R. Balch, Minoru Asada, Silvia Coradeschi, Lars Karlsson, Masahiro Fujita:
Overview of RoboCup-99. RoboCup 1999: 1-34 - [c70]Rajeev Murgai, Jawahar Jain, Masahiro Fujita:
Efficient Scheduling Techniques for ROBDD Construction. VLSI Design 1999: 394-401 - [c69]Ankur Jain, Michael S. Hsiao, Vamsi Boppana, Masahiro Fujita:
On the Evaluation of Arbitrary Defect Coverage of Test Sets. VTS 1999: 426-432 - 1998
- [j12]Masahiro Fujita, Hiroaki Kitano:
Development of an Autonomous Quadruped Robot for Robot Entertainment. Auton. Robots 5(1): 7-18 (1998) - [j11]Sreeranga P. Rajan, Masahiro Fujita, K. Yuan, Mike Tien-Chien Lee:
ATM switch design by high-level modeling, formal verification and high-level synthesis. ACM Trans. Design Autom. Electr. Syst. 3(4): 554-562 (1998) - [c68]Masahiro Fujita, Hiroaki Kitano, Koji Kageyama:
Reconfigurable Physical Agents. Agents 1998: 54-61 - [c67]Juan David Velásquez, Masahiro Fujita, Hiroaki Kitano:
An Open Architecture of Remotion and Behavior Control of Autonomous Agents. Agents 1998: 473-474 - [c66]Masahiro Fujita:
Model Checking: Its Basics and Reality (Embedded Tutorial). ASP-DAC 1998: 217-222 - [c65]Rajeev Murgai, Masahiro Fujita, Arlindo L. Oliveira:
Using Complementation and Resequencing to Minimize Transitions. DAC 1998: 694-697 - [c64]Masahiro Fujita, Sreeranga P. Rajan, Alan J. Hu:
Two Real Formal Verification Experiences: ATM Switch Chip and Parallel Cache Protocol. FM-Trends 1998: 281-295 - [c63]Jawahar Jain, William Adams, Masahiro Fujita:
Sampling schemes for computing OBDD variable orderings. ICCAD 1998: 631-638 - [c62]Hiroaki Kitano, Masahiro Fujita, Stéphane Zrehen, Koji Kageyama:
Sony Legged Robot for RoboCup Challenge. ICRA 1998: 2605-2612 - [c61]Manuela M. Veloso, William T. B. Uther, Masahiro Fujita, Minoru Asada, Hiroaki Kitano:
Playing soccer with legged robots. IROS 1998: 437-442 - [c60]Vamsi Boppana, Masahiro Fujita:
Modeling the unknown! Towards model-independent fault and error diagnosis. ITC 1998: 1094-1101 - [c59]Masahiro Fujita, Stéphane Zrehen, Hiroaki Kitano:
A Quadruped Robot for RoboCup Legged Robot Challenge in Paris '98. RoboCup 1998: 125-140 - [c58]Sreeranga P. Rajan, Masahiro Fujita:
Integration of High-Level Modeling, Formal Verification, and High-Level Synthesis in ATM Switch Design. VLSI Design 1998: 552-557 - 1997
- [j10]Mike Tien-Chien Lee, Yu-Chin Hsu, Ben Chen, Masahiro Fujita:
Domain-Specific High-Level Modeling and Synthesis for ATM Switch Prototyping. Des. Autom. Embed. Syst. 2(3-4): 319-338 (1997) - [j9]Masahiro Fujita, Patrick C. McGeer:
Introduction to the Special Issue on Multi-Terminal Binary Decision Diagrams. Formal Methods Syst. Des. 10(2/3): 135-136 (1997) - [j8]Edmund M. Clarke, Kenneth L. McMillan, Xudong Zhao, Masahiro Fujita, Jerry Chih-Yuan Yang:
Spectral Transforms for Large Boolean Functions with Applications to Technology Mapping. Formal Methods Syst. Des. 10(2/3): 137-148 (1997) - [j7]Masahiro Fujita, Patrick C. McGeer, Jerry Chih-Yuan Yang:
Multi-Terminal Binary Decision Diagrams: An Efficient Data Structure for Matrix Representation. Formal Methods Syst. Des. 10(2/3): 149-169 (1997) - [j6]Mike Tien-Chien Lee, Vivek Tiwari, Sharad Malik, Masahiro Fujita:
Power analysis and minimization techniques for embedded DSP software. IEEE Trans. Very Large Scale Integr. Syst. 5(1): 123-135 (1997) - [c57]Masahiro Fujita, Koji Kageyama:
An Open Architecture for Robot Entertainment. Agents 1997: 435-442 - [c56]Sreeranga P. Rajan, Masahiro Fujita:
ATM Switch Design: Parametric High-Level Modeling and Formal Verification. AMAST 1997: 437-450 - [c55]Rajat Aggarwal, Rajeev Murgai, Masahiro Fujita:
Speeding up technology-independent timing optimization by network partitioning. ICCAD 1997: 83-90 - [c54]Alan J. Hu, Masahiro Fujita, Chris Wilson:
Formal Verification of the HAL S1 System Cache Coherence Protocol. ICCD 1997: 438-444 - [c53]Jawahar Jain, Amit Narayan, Masahiro Fujita, Alberto L. Sangiovanni-Vincentelli:
A Survey of Techniques for Formal Verification of Combinational Circuits. ICCD 1997: 445-454 - [c52]Masahiro Fujita, Koji Kageyama:
A proposal of a quadruped robot platform for RoboCup. IROS 1997 - [c51]Masahiro Fujita, Hiroaki Kitano, Koji Kageyama:
A Legged Robot for RoboCup Based on "OPENR". RoboCup 1997: 168-180 - [c50]Jawahar Jain, Amit Narayan, Masahiro Fujita, Alberto L. Sangiovanni-Vincentelli:
Formal Verification of Combinational Circuit. VLSI Design 1997: 218-225 - [c49]Rajeev Murgai, Masahiro Fujita:
Some Recent Advances in Software and Hardware Logic Simulation. VLSI Design 1997: 232-238 - 1996
- [j5]Kiyoshi Ohishi, Masaru Miyazaki, Masahiro Fujita:
Hybrid Position and Force Control Without Force Sensor. J. Robotics Mechatronics 8(3): 226-234 (1996) - [j4]Robert J. Carragher, Chung-Kuan Cheng, Xiao-Ming Xiong, Masahiro Fujita, Ramamohan Paturi:
Solving the net matching problem in high-performance chip design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(8): 902-911 (1996) - [c48]Masahiro Fujita:
Verification of Arithmetic Circuits by Comparing Two Similar Circuits. CAV 1996: 159-168 - [c47]Mike Tien-Chien Lee, Yu-Chin Hsu, Ben Chen, Masahiro Fujita:
Domain-Specific High-Level Modeling and Synthesis for ATM Switch Design Using VHDL. DAC 1996: 585-590 - [c46]Jawahar Jain, Amit Narayan, C. Coelho, Sunil P. Khatri, Alberto L. Sangiovanni-Vincentelli, Robert K. Brayton, Masahiro Fujita:
Decomposition Techniques for Efficient ROBDD Construction. FMCAD 1996: 419-434 - [c45]Amit Narayan, Jawahar Jain, Masahiro Fujita, Alberto L. Sangiovanni-Vincentelli:
Partitioned ROBDDs - a compact, canonical and efficiently manipulable representation for Boolean functions. ICCAD 1996: 547-554 - [c44]Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita, Jacob A. Abraham, Donald S. Fussell:
On More Efficient Combinational ATPG Using Functional Learning. VLSI Design 1996: 107-110 - [c43]Amit Narayan, Sunil P. Khatri, Jawahar Jain, Masahiro Fujita, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
A study of composition schemes for mixed apply/compose based construction of ROBDDs. VLSI Design 1996: 249-253 - 1995
- [c42]Jawahar Jain, Rajarshi Mukherjee, Masahiro Fujita:
Advanced Verification Techniques Based on Learning. DAC 1995: 420-426 - [c41]Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita:
VERIFUL: VERIfication using FUnctional Learning. ED&TC 1995: 444-448 - [c40]Edmund M. Clarke, Masahiro Fujita, Xudong Zhao:
Hybrid decision diagrams. ICCAD 1995: 159-163 - [c39]Rajeev Murgai, Masahiro Fujita, Fumiyasu Hirose:
Logic synthesis for a single large look-up table. ICCD 1995: 415-424 - [c38]Robert J. Carragher, Masahiro Fujita, Chung-Kuan Cheng:
Simple tree-construction heuristics for the fanout problem . ICCD 1995: 671-679 - [c37]Mike Tien-Chien Lee, Vivek Tiwari, Sharad Malik, Masahiro Fujita:
Power analysis and low-power scheduling techniques for embedded DSP software. ISSS 1995: 110-115 - 1994
- [c36]Ben Chen, Michihiro Yamazaki, Masahiro Fujita:
Bug Identification of a Real Chip Design by Symbolic Model Checking. EDAC-ETC-EUROASIC 1994: 132-136 - [c35]Yutaka Tamiya, Yusuke Matsunaga, Masahiro Fujita:
LP based cell selection with constraints of timing, area, and power consumption. ICCAD 1994: 378-381 - [c34]Yuji Kukimoto, Masahiro Fujita, Robert K. Brayton:
A redesign technique for combinational circuits based on gate reconnections. ICCAD 1994: 632-637 - [c33]Hitomi Sato, Michihiro Yamazaki, Masahiro Fujita:
YEPHCAD and FLORA: Logic Synthesis for Control and Datapath. ICCD 1994: 527-530 - [c32]Masahiro Fujita, Jerry Chih-Yuan Yang, Edmund M. Clarke, Xudong Zhao, Patrick C. McGeer:
Fast Spectrum Computation for Logic Functions using Binary Decision Diagrams. ISCAS 1994: 275-278 - 1993
- [j3]Masahiro Fujita, Hisanori Fujisawa, Yusuke Matsunaga:
Variable ordering algorithms for ordered binary decision diagrams and their evaluation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(1): 6-12 (1993) - [c31]Edmund M. Clarke, Kenneth L. McMillan, Xudong Zhao, Masahiro Fujita, Jerry Chih-Yuan Yang:
Spectral Transforms for Large Boolean Functions with Applications to Technology Mapping. DAC 1993: 54-60 - [c30]Robert J. Carragher, Chung-Kuan Cheng, Masahiro Fujita:
An efficient algorithm for the net matching problem. ICCAD 1993: 640-644 - [c29]Masahiro Fujita, Shinji Kono:
Synthesis of Controllers from Interval Temporal Logic Specification. ICCD 1993: 242-245 - [c28]Takeshi Sakaguchi, Masahiro Fujita, Hiroshi Watanabe, Fumio Miyazaki:
Motion Planning and Control for a Robot Performer. ICRA (3) 1993: 925-931 - 1992
- [c27]Kuang-Chien Chen, Masahiro Fujita:
Efficient Sum-to-One Subsets Algorithm for Logic Optimization. DAC 1992: 443-448 - [c26]Masahiro Fujita, Yuji Kukimoto:
Patching Method for Lookup-Table Type FPLs. FPL 1992: 61-70 - [c25]Yuji Kukimoto, Masahiro Fujita:
Rectification method for lookup-table type FPGA's. ICCAD 1992: 54-61 - [c24]Masahiro Fujita:
RTL Design Verification by Making Use of Datapath Information. ICCD 1992: 592-597 - [c23]Kiyoshi Ohishi, Masaru Miyazaki, Masahiro Fujita, Yasumasa Ogino:
Force control without force sensor based on mixed sensitivity H ∞ design method. ICRA 1992: 1356-1361 - 1991
- [c22]Kuang-Chien Chen, Yusuke Matsunaga, Saburo Muroga, Masahiro Fujita:
A Resynthesis Approach for Network Optimization. DAC 1991: 458-463 - [c21]Masahiro Fujita, Yusuke Matsunaga, Taeko Kakuda:
On variable ordering of binary decision diagrams for the application of multi-level logic synthesis. EURO-DAC 1991: 50-54 - [c20]Masahiro Fujita, Yutaka Tamiya, Yuji Kukimoto, Kuang-Chien Chen:
Application of Boolean Unification to Combinational Logic Synthesis. ICCAD 1991: 510-513 - [c19]Masahiro Fujita, Yusuke Matsunaga:
Multi-Level Logic Minimization Based on Minimal Support and its Application to the Minimization of Look-Up Table Type FPGAs. ICCAD 1991: 560-563 - [c18]Kuang-Chien Chen, Masahiro Fujita:
Concurrent Resynthesis for Network Optimization. ICCD 1991: 44-48 - [c17]Zhen-Ping Lo, Masahiro Fujita, Behnam Bavarian:
Analysis of Neighborhood Interaction in Kohonen Neural Networks. IPPS 1991: 246-249 - 1990
- [j2]Hitomi Sato, Yoshihide Sugiura, Masahiro Fujita:
Speed tunable finite state machine compiler: Zephcad. Microprocess. Microsystems 14(1): 17-20 (1990) - [c16]Atsunobu Hiraiwa, Masahiro Fujita, Shigeru Kurosu, Shigeru Arisawa, Makoto Inoue:
Implementation of ANN on RISC processor array. ASAP 1990: 677-688 - [c15]Hiroshi Nakamura, Yuji Kukimoto, Masahiro Fujita, Hidehiko Tanaka:
A Data Path Verifier for Register Transfer Level Using Temporal Logic Language Tokio. CAV 1990: 76-85 - [c14]Hitomi Sato, Yoshihiro Yasue, Yusuke Matsunaga, Masahiro Fujita:
Boolean Resubstitution with Permissible Functions and Binary Decision Diagrams. DAC 1990: 284-289 - [c13]Hiroshi Nakamura, Yuji Kukimoto, Masahiro Fujita, Hidehiko Tanaka:
A Data Path Verifier for Register Transfer Level Using Temporal Logic Language Tokio. CAV (DIMACS/AMS volume) 1990: 493-504 - [c12]Masahiro Fujita, Yusuke Matsunaga, Takeo Kakuda:
Automatic and Semi-Automatic Verification of Switch-Level Circuits with Temporal Logic and Binary Decision Diagrams. ICCAD 1990: 38-41 - [c11]Yusuke Matsunaga, Masahiro Fujita, Takeo Kakuda:
Multi-Level Logic Minimization Across Latch Boundaries. ICCAD 1990: 406-409 - [c10]Hiroshi Nakamura, Yuji Kukimoto, Masahiro Fujita, Hidehiko Tanaka:
Practical design assistance at register transfer level using a data path verifier. ICCD 1990: 99-102 - [c9]Hitomi Sato, Norikazu Takahashi, Yusuke Matsunaga, Masahiro Fujita:
Boolean technology mapping for both ECI and CMOS circuits based on permissible functions and binary decision diagrams. ICCD 1990: 286-290
1980 – 1989
- 1989
- [c8]Yusuke Matsunaga, Masahiro Fujita:
Multi-level logic optimization using binary decision diagrams. ICCAD 1989: 556-559 - [c7]Hiroshi Nakamura, Masaya Nakai, Shinji Kono, Masahiro Fujita, Hidehiko Tanaka:
Logic Design Assistence Using Temporal Logic Based Language Tokio. LP 1989: 174-183 - 1988
- [c6]Masahiro Fujita, Hisanori Fujisawa, Nobuaki Kawato:
Evaluation and improvement of Boolean comparison method based on binary decision diagrams. ICCAD 1988: 2-5 - 1986
- [c5]Masahiro Fujita, Shinji Kono, Hidehiko Tanaka, Tohru Moto-Oka:
Tokio: Logic Programming Language Based on Temporal Logic and its Compilation to Prolog. ICLP 1986: 695-709 - 1985
- [c4]T. Aoyagi, Masahiro Fujita, Tohru Moto-Oka:
Temporal Logic Programming Language Tokio - Programming in Tokio. LP 1985: 128-137 - [c3]Shinji Kono, T. Aoyagi, Masahiro Fujita, Hidehiko Tanaka:
Implementation of Temporal Logic Programming Language Tokio. LP 1985: 138-147 - [c2]Masahiro Fujita, Makoto Ishisone, Hiroshi Nakamura, Hidehiko Tanaka, Tohru Moto-Oka:
Using the Temporal Logic Programming Language Tokio for Algorithm Description and Automatic CMOS Gate Array Synthesis. LP 1985: 246-255 - 1984
- [c1]Masahiro Fujita, Hidehiko Tanaka, Tohru Moto-Oka:
Specifying Hardware in temporal Logic & Efficient Synthesis of State-Diagrams Using Prolog. FGCS 1984: 572-581 - 1983
- [j1]Masahiro Fujita, Hidehiko Tanaka, Tohru Moto-Oka:
Temporal Logic Based Hardware Description and Its Verification with Prolog. New Gener. Comput. 1(2): 195-203 (1983)
Coauthor Index
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Citation data
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load citations from opencitations.net
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OpenAlex data
Load additional information about publications from 
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last updated on 2024-10-30 20:32 CET by the dblp team
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