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ORCIDMEMSYS 2015: Washington, DC, USA
- Bruce L. Jacob:
Proceedings of the 2015 International Symposium on Memory Systems, MEMSYS 2015, Washington DC, DC, USA, October 5-8, 2015. ACM 2015, ISBN 978-1-4503-3604-8
Opportunities and Challenges
- Gabriel H. Loh, Natalie D. Enright Jerger
, Ajaykumar Kannan, Yasuko Eckert:
Interconnect-Memory Challenges for Multi-chip, Silicon Interposer Systems. 3-10 - Syed Minhaj Hassan, Sudhakar Yalamanchili, Saibal Mukhopadhyay:
Near Data Processing: Impact and Optimization of 3D Memory System Architecture on the Uncore. 11-21 - Marco A. Z. Alves, Paulo C. Santos, Matthias Diener, Luigi Carro:
Opportunities and Challenges of Performing Vector Operations inside the DRAM. 22-28 - Chad D. Kersey, Sudhakar Yalamanchili, Hyesoon Kim:
SIMT-based Logic Layers for Stacked DRAM Architectures: A Prototype. 29-30 - Milan Radulovic, Darko Zivanovic, Daniel Ruiz, Bronis R. de Supinski, Sally A. McKee, Petar Radojkovic, Eduard Ayguadé:
Another Trip to the Wall: How Much Will Stacked DRAM Benefit HPC? 31-36
Rethinking Architectures and Design Approaches
- Yitzhak Birk, Oskar Mencer:
A Data Centric Perspective on Memory Placement. 39-42 - Jim Stevens, Paul Tschirhart, Bruce L. Jacob:
The Semantic Gap Between Software and the Memory System. 43-46 - Chen Ding, Hao Lu, Chencheng Ye:
MMC: a Many-core Memory Connection Model. 47-50 - James Andrew Ang:
High Performance Computing Co-Design Strategies. 51-52
The Devil is in the Details
- Dave Resnick:
Opportunities to Upgrade Main Memory. 55-59 - Hsing Min Chen, Akhil Arunkumar, Carole-Jean Wu, Trevor N. Mudge, Chaitali Chakrabarti:
E-ECC: Low Power Erasure and Error Correction Schemes for Increasing Reliability of Commodity DRAM Systems. 60-70 - Ali Eslami, Alfredo Velasco, Alireza Vahid, Georgios Mappouras, A. Robert Calderbank, Daniel J. Sorin:
Writing without Disturb on Phase Change Memories by Integrating Coding and Layout Design. 71-77 - Bruce R. Childers, Jun Yang, Youtao Zhang:
Achieving Yield, Density and Performance Effective DRAM at Extreme Technology Sizes. 78-84 - Matthias Jung, Éder Zulian, Deepak M. Mathew, Matthias Herrmann, Christian Brugger, Christian Weis, Norbert Wehn:
Omitting Refresh: A Case Study for Commodity and Wide I/O DRAMs. 85-91
Caches and Software Management of Memory
- Brian Kocoloski, Yuyu Zhou, Bruce R. Childers, John R. Lange:
Implications of Memory Interference for Composed HPC Applications. 95-97 - Paul Sebexen, Thomas Sohmers:
Software Techniques for Scratchpad Memory Management. 98-102 - Jinchun Kim, Viacheslav V. Fedorov, Paul V. Gratz, A. L. Narasimha Reddy:
Dynamic Memory Pressure Aware Ballooning. 103-112 - Viacheslav V. Fedorov, A. L. Narasimha Reddy, Paul V. Gratz:
Shared Last-Level Caches and The Case for Longer Timeslices. 113-120 - Reza Mokhtari, Michael Stumm:
S-L1: A Software-based GPU L1 Cache that Outperforms the Hardware L1 for Data Processing Applications. 121-132
Design and Simulation Methodologies
- Fernando Martin del Campo, Paul Chow:
Architecture Exploration for Data Intensive Applications. 135-145 - Ganesh Balakrishnan, Yan Solihin:
MEMST: Cloning Memory Behavior using Stochastic Traces. 146-157 - Aditya M. Deshpande, Jeffrey T. Draper:
Modeling Data Movement in the Memory Hierarchy in HPC Systems. 158-161 - Manu Awasthi:
Rethinking Design Metrics for Datacenter DRAM. 162-163
Multi-Level and Hybrid Main Memories
- Chun-Yi Su, David Roberts, Edgar A. León, Kirk W. Cameron, Bronis R. de Supinski, Gabriel H. Loh, Dimitrios S. Nikolopoulos:
HpMC: An Energy-aware Management System of Multi-level Memory Architectures. 167-178 - Paul Tschirhart, Jim Stevens, Zeshan Chishti, Shih-Lien Lu, Bruce L. Jacob:
Bringing Modern Hierarchical Memory Systems Into Focus: A study of architecture and workload factors on system performance. 179-190 - Jagan Jayaraj, Arun F. Rodrigues, Simon D. Hammond, Gwendolyn R. Voskuilen:
The Potential and Perils of Multi-Level Memory. 191-196 - Michael A. Bender, Jonathan W. Berry, Simon D. Hammond, Branden Moore, Benjamin Moseley, Cynthia A. Phillips:
k-Means Clustering on Two-Level Memory Systems. 197-205 - Ahsen J. Uppal, Mitesh R. Meswani:
Towards Workload-Aware Page Cache Replacement Policies for Hybrid Memories. 206-219
A Focus on Applications
- Adwait Jog, Onur Kayiran, Tuba Kesten, Ashutosh Pattnaik, Evgeny Bolotin, Niladrish Chatterjee, Stephen W. Keckler, Mahmut T. Kandemir, Chita R. Das:
Anatomy of GPU Memory System for Multi-Application Execution. 223-234 - Anouk Van Laer, William Wang, Christopher D. Emmons:
Inefficiencies in the Cache Hierarchy: A Sensitivity Study of Cacheline Size with Mobile Workloads. 235-245 - Zhaoxia Deng, Lunkai Zhang, Diana Franklin, Frederic T. Chong:
Herniated Hash Tables: Exploiting Multi-Level Phase Change Memory for In-Place Data Expansion. 247-257 - Lifeng Nai, Hyesoon Kim:
Instruction Offloading with HMC 2.0 Standard: A Case Study for Graph Traversals. 258-261
Systems and Techniques for In-Memory Processing
- I. Stephen Choi, Yang-Suk Kee:
Energy Efficient Scale-In Clusters with In-Storage Processing for Big-Data Analytics. 265-273 - Carlo C. del Mundo, Vincent T. Lee, Luis Ceze, Mark Oskin:
NCAM: Near-Data Processing for Nearest Neighbor Search. 274-275 - Hyojong Kim, Hyesoon Kim, Sudhakar Yalamanchili, Arun F. Rodrigues:
Understanding Energy Aspects of Processing-near-Memory for HPC Workloads. 276-282 - Maya B. Gokhale, G. Scott Lloyd, Chris Hajas:
Near memory data structure rearrangement. 283-290
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