default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID25th MICRO 1992: Portland, Oregon, USA
- Wen-mei W. Hwu:
Proceedings of the 25th Annual International Symposium on Microarchitecture, Portland, Oregon, USA, November 1992. ACM / IEEE Computer Society 1992, ISBN 0-8186-3175-9 - Michael Butler, Yale N. Patt:
An investigation of the performance of various dynamic scheduling techniques. 1-9 - Kevin B. Theobald, Guang R. Gao, Laurie J. Hendren:
On the limits of program parallelism and its smoothability. 10-19 - Sriram Vajapeyam, Wei-Chung Hsu:
On the instruction-level characteristics of scalar code in highly-vectorized scientific applications. 20-28 - Meng-chou Chang, Feipei Lai, Rung-Ji Shang:
Exploiting instruction-level parallelism with the conjugate register file scheme. 29-32 - Thang Tran, Chuan-lin Wu:
Limitation of superscalar microprocessor performance. 33-36 - Chien-Ming Chen, Yunn Yen Chen, Chung-Ta King:
Branch merging for effective exploitation of instruction-level parallelism. 37-40 - Alessandro De Gloria, Paolo Faraboschi, Mauro Olivieri:
A non-deterministic scheduler for a software pipelining compiler. 41-44 - Scott A. Mahlke, David C. Lin, William Y. Chen, Richard E. Hank, Roger A. Bringmann:
Effective compiler support for predicated execution using the hyperblock. 45-54 - Soo-Mook Moon, Kemal Ebcioglu:
An efficient resource-constrained global scheduling technique for superscalar and VLIW processors. 55-71 - V. H. Allen, J. Janardhan, R. M. Lee, M. Srinivas:
Enhanced region scheduling on a program dependence graph. 72-80 - Andrew Wolfe, Alex Chanin:
Executing compressed programs on an embedded RISC architecture. 81-91 - William Y. Chen, Roger A. Bringmann, Scott A. Mahlke, Richard E. Hank, James E. Sicolo:
An efficient architecture for loop based data preloading. 92-101 - John W. C. Fu, Janak H. Patel, Bob L. Janssens:
Stride directed prefetching in scalar processors. 102-110 - André Seznec, Karl Courtel:
Controlling and sequencing a heavily pipelined floating-point operator. 111-114 - Augustus K. Uht, Darin B. Johnson:
Data path issues in a highly concurrent machine. 115-118 - Bogong Su, Wei Zhao, Zhizhong Tang, Stanley Habib:
A VLIW architecture for optimal execution of branch-intensive loops. 119-124 - Michael J. Knieser, Christos A. Papachristou:
Y-Pipe: a conditional branching scheme without pipeline delays. 125-128 - Tse-Yu Yeh, Yale N. Patt:
A comprehensive instruction fetch mechanism for a processor supporting speculative execution. 129-139 - Carl J. Beckmann, Constantine D. Polychronopoulos:
Microarchitecture support for dynamic scheduling of acyclic task graphs. 140-148 - Nadeem Malik, Richard J. Eickemeyer, Stamatis Vassiliadis:
Interlock collapsing ALU for increased instruction-level parallelism. 149-157 - B. Ramakrishna Rau, Michael S. Schlansker, Parthasarathy P. Tirumalai:
Code generation schema for modulo scheduled loops. 158-169 - Nancy J. Warter, Grant E. Haab, Krishna Subramanian, John W. Bockhaus:
Enhanced modulo scheduling for loops with conditional branches. 170-179 - Steven R. Vegdahl:
A dynamic-programming technique for compacting loops. 180-188 - Philip LeNir, Ramaswamy Govindarajan, Shashank S. Nemawarkar:
Exploiting instruction-level parallelism: the multithreaded approach. 189-192 - Gary S. Tyson, Matthew K. Farrens, Andrew R. Pleszkun:
MISC: a Multiple Instruction Stream Computer. 193-196 - Tokuzo Kiyohara, John C. Gyllenhaal:
Code scheduling for VLIW/superscalar processors with limited register files. 197-201 - Thomas M. Conte
:
Tradeoffs in processor/memory interfaces for superscalar processors. 202-205 - Brian K. Bray, Michael J. Flynn:
Translation hint buffers to reduce access time of physically-addressed instruction caches. 206-209 - Matthew K. Farrens, Arvin Park, Gary S. Tyson:
Modifying VM hardware to reduce address pin requirements. 210-213 - Kent D. Wilken, David W. Goodwin:
Toward zero-cost branches using instruction registers. 214-217 - Youfeng Wu:
Ordering functions for improving memory reference locality in a shared memory multiprocessor system. 218-221 - William L. Lynch, Brian K. Bray, Michael J. Flynn:
The effect of page allocation on caches. 222-225 - David Bernstein, Doron Cohen, Yuval Lavon, Vladimir Rainish:
Performance evaluation of instruction scheduling on the IBM RISC System/6000. 226-235 - Manoj Franklin, Gurindar S. Sohi:
Register traffic analysis for streamlining inter-operation communication in fine-grain parallel processors. 236-245 - Takaaki Kato, Toshihisa Ono, Nader Bagherzadeh:
Performance analysis and design methodology for a scalable superscalar architecture. 246-255 - Steven J. Beaty:
Lookahead scheduling. 256-259 - Philip H. Sweany, Steven J. Beaty:
Dominator-path scheduling: a global scheduling method. 260-263 - Brian A. Malloy, Rajiv Gupta, Mary Lou Soffa:
A shape matching approach for scheduling fine-grained parallelism. 264-267 - Shih-Hsu Huang, Cheng-Tsung Hwang, Yu-Chin Hsu, Yen-Jen Oyang:
A new approach to schedule operations across nested-ifs and nested-loops. 268-271 - Harry Dwyer, Hwa C. Torng:
An out-of-order superscalar processor with speculative execution and fast, precise interrupts. 272-281 - Benoît Dupont de Dinechin:
StaCS: a Static Control Superscalar architecture. 282-291 - Andrea Capitanio, Nikil D. Dutt, Alexandru Nicolau:
Partitioned register files for VLIWs: a preliminary analysis of tradeoffs. 292-300
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-06-19 01:21 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
