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ORCID24th MICRO 1991: Albuquerque, New Mexico, USA
- Yashwant K. Malaiya:
Proceedings of the 24th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 24, Albuquerque, New Mexico, USA, November 18-20, 1991. ACM/IEEE 1991, ISBN 0-89791-460-0 - Michael A. Schuette, John Paul Shen:
An Instruction-Level Performance Analysis of the Multiflow TRACE 14/300. 2-11 - William Marcus Miller, Walid A. Najjar
, A. P. Wim Böhm:
A Quantitative Analysis of Locality in Dataflow Programs. 12-18 - Jeffrey C. Becker, Arvin Park, Matthew K. Farrens:
An Analysis of the Information Content of Address Reference Streams. 19-24 - Pohua P. Chang, William Y. Chen, Scott A. Mahlke, Wen-mei W. Hwu:
Comparing Static and Dynamic Code Scheduling for Multiple-Instruction-Issue Processors. 25-33 - Michael Butler, Yale N. Patt:
The Effect of Real Data Cache Behavior on the Performance of a Microarchitecture that Supports Dynamic Scheduling. 34-41 - Brian K. Bray, Michael J. Flynn:
Strategies for Branch Target Buffers. 42-50 - Tse-Yu Yeh, Yale N. Patt:
Two-Level Adaptive Training Branch Prediction. 51-61 - Matthew K. Farrens, Arvin Park:
Workload and Implementation Considerations for Dynamic Base Register Caching. 62-68 - William Y. Chen, Scott A. Mahlke, Pohua P. Chang, Wen-mei W. Hwu:
Data Access Microarchitectures for Superscalar Processors with Compiler-Assisted Data Prefetching. 69-73 - Jan Hoogerbrugge, Henk Corporaal, Hans M. Mulder:
Software Pipelining for Transport-Triggered Architectures. 74-81 - Reese B. Jones, Vicki H. Allan:
Software Pipelining: An Evaluation of Enhanced Pipelining. 82-92 - Mark Smotherman, Sanjay Krishnamurthy, P. S. Aravind, David Hunnicutt:
Efficient DAG Construction and Heuristic Calculation for Instruction Scheduling. 93-102 - David Bernstein, Doron Cohen, Hugo Krawczyk:
Code Duplication: An Assist for Global Instruction Scheduling. 103-113 - Maurício Breternitz Jr., John Paul Shen:
Implementation Optimization Techniques for Architecture Synthesis of Application-Specific Processors. 114-123 - Ramesh Karri, Alex Orailoglu:
ALPS: An Algorithm for Pipeline Data Path Synthesis. 124-132 - Robert A. Walker, Shivkumar Ramabadran, Rajive Joshi, Steinar Flatland:
Increasing User Interaction During High-Level Synthesis. 133-142 - Gautam B. Singh:
GRIP: Graphics Reduced Instruction Processor. 143-152 - Bruce K. Holmer, Alvin M. Despain:
Viewing Instruction Set Design as an Optimization Problem. 153-162 - Mario Nemirovsky, Forrest Brewer, Roger C. Wood:
DISC: Dynamic Instruction Stream Computer. 163-171 - Haigeng Wang, Alexandru Nicolau, Roni Potasman:
A New Technique for Induction Variable Removal. 172-180 - Gerben Essink, Emile H. L. Aarts, R. van Dongen, Piet J. van Gerwen, Jan H. M. Korst, Kees A. Vissers:
Architecture and Programming of a VLIW Style Programmable Video Signal Processor. 181-188 - Fredrik Dahlgren, Per Stenström:
On Reconfigurable On-Chip Data Caches. 189-198 - Sunah Lee, Rajiv Gupta:
Executing Loops on a Fine-Grained MIMD Architecture. 199-205 - Steven J. Beaty:
Genetic Algorithms and Instruction Scheduling. 206-211 - Bogong Su, Jian Wang:
GURPR*: A New Global Software Pipelining Algorithm. 212-216 - Samarina Makhdoom, Daniel Tabak, Richard Auletta:
Register/File/Cache Microarchitecture Study Using VHDL. 217-222
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