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ORCIDPohua P. Chang
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1990 – 1999
- 1998
[c19]Pohua P. Chang, Scott A. Mahlke, William Y. Chen, Nancy J. Warter, Wen-mei W. Hwu:
IMPACT: An Architectural Framework for Multiple-Instruction-Issue Processors. 25 Years ISCA: Retrospectives and Reprints 1998: 408-417- 1996
- [j8]Po-Yung Chang, Eric Hao, Yale N. Patt, Pohua P. Chang:
Using Predicated Execution to Improve the Performance of a Dynamically Scheduled Machine with Speculative Execution. Int. J. Parallel Program. 24(3): 209-234 (1996) - [c18]David A. Berson, Pohua P. Chang, Rajiv Gupta
, Mary Lou Soffa:
Integrating Program Optimizations and Transformations with the Scheduling of Instruction Level Parallelism. LCPC 1996: 207-221 - [c17]Pohua P. Chang, Dong-yuan Chen, Yong-Fong Lee, Youfeng Wu, Utpal Banerjee:
Bidirectional Scheduling: A New Global Code Scheduling Approach. LCPC 1996: 222-230 - [c16]K. Sridharan, Pohua P. Chang, Utpal Banerjee, Ravi Narayanaswamy, Suresh Rao:
Memory Optimizations in the Intel Reference Compiler. LCPC 1996: 608-610 - 1995
- [j7]Pohua P. Chang, Daniel M. Lavery, Scott A. Mahlke, William Y. Chen, Wen-mei W. Hwu:
The Importance of Prepass Code Scheduling for Superscalar and Superpipelined Processors. IEEE Trans. Computers 44(3): 353-370 (1995) - [j6]Pohua P. Chang, Nancy J. Warter, Scott A. Mahlke, William Y. Chen, Wen-mei W. Hwu:
Three Architecutral Models for Compiler-Controlled Speculative Execution. IEEE Trans. Computers 44(4): 481-494 (1995) - [c15]Po-Yung Chang, Eric Hao, Yale N. Patt, Pohua P. Chang:
Using predicated execution to improve the performance of a dynamically scheduled machine with speculative execution. PACT 1995: 99-108 - [c14]Pohua P. Chang, Utpal Banerjee:
Profile-Guided Multi-Heuristic Branch Prediction. ICPP (1) 1995: 215-218 - [c13]James Radigan, Pohua P. Chang, Utpal Banerjee:
Integer Loop Code Generation for VLIW. LCPC 1995: 318-330 - 1994
- [c12]Pohua P. Chang:
Introduction. HICSS (1) 1994: 360 - 1993
- [j5]William Y. Chen, Pohua P. Chang, Thomas M. Conte, Wen-mei W. Hwu:
The Effect of Code Expanding Optimizations on Instruction Cache Design. IEEE Trans. Computers 42(9): 1045-1057 (1993) - [j4]Wen-mei W. Hwu, Scott A. Mahlke, William Y. Chen, Pohua P. Chang, Nancy J. Warter, Roger A. Bringmann, Roland G. Ouellette, Richard E. Hank, Tokuzo Kiyohara, Grant E. Haab, John G. Holm, Daniel M. Lavery:
The superblock: An effective technique for VLIW and superscalar compilation. J. Supercomput. 7(1-2): 229-248 (1993) - 1992
- [j3]Pohua P. Chang, Scott A. Mahlke, William Y. Chen, Wen-mei W. Hwu:
Profile-guided Automatic Inline Expansion for C Programs. Softw. Pract. Exp. 22(5): 349-369 (1992) - [j2]Wen-mei W. Hwu, Pohua P. Chang:
Efficient Instruction Sequencing with Inline Target Insertion. IEEE Trans. Computers 41(12): 1537-1551 (1992) - [c11]William Y. Chen, Scott A. Mahlke, Wen-mei W. Hwu, Tokuzo Kiyohara, Pohua P. Chang:
Tolerating data access latency with register preloading. ICS 1992: 104-113 - 1991
- [j1]Pohua P. Chang, Scott A. Mahlke, Wen-mei W. Hwu:
Using Profile Information to Assist Classic Code Optimizations. Softw. Pract. Exp. 21(12): 1301-1321 (1991) - [c10]Scott A. Mahlke, Nancy J. Warter, William Y. Chen, Pohua P. Chang, Wen-mei W. Hwu:
The Effect of Compiler Optimizations on Available Parallelism in Scalar Programs. ICPP (2) 1991: 142-145 - [c9]Pohua P. Chang, Scott A. Mahlke, William Y. Chen, Nancy J. Warter, Wen-mei W. Hwu:
IMPACT: An Architectural Framework for Multiple-Instruction-Issue Processors. ISCA 1991: 266-275 - [c8]Pohua P. Chang, William Y. Chen, Scott A. Mahlke, Wen-mei W. Hwu:
Comparing Static and Dynamic Code Scheduling for Multiple-Instruction-Issue Processors. MICRO 1991: 25-33 - [c7]William Y. Chen, Scott A. Mahlke, Pohua P. Chang, Wen-mei W. Hwu:
Data Access Microarchitectures for Superscalar Processors with Compiler-Assisted Data Prefetching. MICRO 1991: 69-73
1980 – 1989
- 1989
- [c6]Pohua P. Chang, Wen-mei W. Hwu:
Control flow optimization for supercomputer scalar processing. ICS 1989: 145-153 - [c5]Wen-mei W. Hwu, Thomas M. Conte, Pohua P. Chang:
Comparing Software and Hardware Schemes For Reducing the Cost of Branches. ISCA 1989: 224-233 - [c4]Wen-mei W. Hwu, Pohua P. Chang:
Achieving High Instruction Cache Performance with an Optimizing Compiler. ISCA 1989: 242-251 - [c3]Wen-mei W. Hwu, Pohua P. Chang:
Inline Function Expansion for Compiling C Programs. PLDI 1989: 246-257 - 1988
- [c2]Wen-mei W. Hwu, Pohua P. Chang:
Exploiting Parallel Microprocessor Microarchitectures With a Compiler Code Generator. ISCA 1988: 45-53 - [c1]Pohua P. Chang, Wen-mei W. Hwu:
Trace selection for compiling large C application programs to microcode. MICRO 1988: 21-29
Coauthor Index
aka: Wen-mei W. Hwu
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