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ORCIDNoCArc@MICRO 2010: Atlanta, Georgia, USA
- Maurizio Palesi, Shashi Kumar, Zhonghai Lu, Ümit Y. Ogras:
Third International Workshop on Network on Chip Architectures, NoCArc'10, Atlanta, GA, USA, December 4, 2010. ACM 2010, ISBN 978-1-4503-0397-2
Keynote talk
- Ganapati Srinivasa:
Evolution of the server processor/platform architecture and the critical role of interconnect and future challenges. 1
QoS and fault tolerance for NoC architectures
- Yuho Jin, Ruisheng Wang, Woojin Choi, Timothy Mark Pinkston:
Thread criticality support in on-chip networks. 5-10 - Chaochao Feng, Zhonghai Lu, Axel Jantsch
, Jinwen Li, Minxuan Zhang:
A reconfigurable fault-tolerant deflection routing algorithm based on reinforcement learning for network-on-chip. 11-16 - Daniele Mangano, Giovanni Strano:
Enabling dynamic and programmable QoS in SoCs. 17-22
Frameworks for NoC design and monitoring
- Leandro Fiorin, Gianluca Palermo, Cristina Silvano:
A monitoring system for NoCs. 25-30 - Joel Hestness, Boris Grot, Stephen W. Keckler:
Netrace: dependency-driven trace-based network-on-chip simulation. 31-36 - Daniele Ludovici, Georgi Nedeltchev Gaydadjiev, Francisco Gilabert Villamón, María Engracia Gómez, Davide Bertozzi:
Contrasting topologies for regular interconnection networks under the constraints of nanoscale silicon technology. 37-42
Routing and mapping optimization for NoC architectures
- Abbas Eslami Kiasari, Axel Jantsch, Zhonghai Lu:
A framework for designing congestion-aware deterministic routing. 45-50 - Saurabh Agrawal, Dhawal Sant, G. K. Sharma:
An efficient energy- and bandwidth- aware mapping algorithm for regular NoC architecture. 51-55 - Yuto Hirata, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
A variable-pipeline on-chip router optimized to traffic pattern. 57-62
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