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2020 – today
- 2025
[j58]Michihiro Koibuchi:
Foreword. IEICE Trans. Inf. Syst. 108(1): 1 (2025)- [j57]Kenji Mizutani, Yutaka Urino, Takanori Shimizu, Hiroshi Yamaguchi, Shigeru Nakamura, Tatsuya Usuki, Kiyo Ishii, Ryosuke Matsumoto, Takashi Inoue, Shu Namiki, Michihiro Koibuchi:
In-network stable radix sorter using many FPGAs with high-bandwidth photonics [Invited]. J. Opt. Commun. Netw. 17(1): 34 (2025) - 2024
- [c130]Kien Trung Pham, Truong Thao Nguyen, Michihiro Koibuchi:
A Bandwidth-Optimal All-to-All Communication in Two-Dimensional Fully Connected Network. CCGrid 2024: 1-7 - [c129]Yuki Kameyama, Naoya Niwa, Daichi Fujiki, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
The Case for Coherence Directories in Memory Cubes. MCSoC 2024: 187-193 - [c128]Kenji Mizutani, Yutaka Urino, Takanori Shimizu, Hiroshi Yamaguchi, Shigeru Nakamura, Tatsuya Usuki, Kiyo Ishii, Ryosuke Matsumoto, Takashi Inoue, Shu Namiki, Michihiro Koibuchi:
Performance of Radix Sort using All-to-all Optical Interconnection Network in an Eight-FPGA Cluster. OFC 2024: 1-3 - 2023
- [j56]Toshiki Ishimaru, Takatomo Mihana
, Michihiro Koibuchi, Tetsuya Kawanishi, Makoto Naruse:
Experimental Demonstration of Approximate Communication Based on Radio-Over- Fiber Systems. IEEE Access 11: 65590-65598 (2023) - [j55]Ryota Yasudo, Koji Nakano, Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano:
Designing low-diameter interconnection networks with multi-ported host-switch graphs. Concurr. Comput. Pract. Exp. 35(11) (2023) - [j54]Naoya Niwa, Yoshiya Shikama, Hideharu Amano, Michihiro Koibuchi:
A Compression Router for Low-Latency Network-on-Chip. IEICE Trans. Inf. Syst. 106(2): 170-180 (2023) - [j53]Truong Thao Nguyen, Kien Trung Pham, Hiroshi Yamaguchi, Yutaka Urino, Michihiro Koibuchi:
Effective switchless inter-FPGA memory networks. J. Parallel Distributed Comput. 179: 104713 (2023) - [c127]Naoki Shibahara, Michihiro Koibuchi, Hiroki Matsutani:
Performance Improvement of Federated Learning Server using Smart NIC. CANDARW 2023: 165-171 - [c126]Shoichi Hirasawa, Michihiro Koibuchi:
An Auto-Tuning Method for High-Bandwidth Low-Latency Approximate Interconnection Networks. PDP 2023: 9-16 - [i2]Naoki Shibahara, Michihiro Koibuchi, Hiroki Matsutani:
A Case for Offloading Federated Learning Server on Smart NIC. CoRR abs/2307.06561 (2023) - 2022
- [j52]Naoya Niwa, Hideharu Amano, Michihiro Koibuchi:
Boosting the Performance of Interconnection Networks by Selective Data Compression. IEICE Trans. Inf. Syst. 105-D(12): 2057-2065 (2022) - [j51]Kenji Mizutani, Hiroshi Yamaguchi, Yutaka Urino, Michihiro Koibuchi:
Accelerating parallel data processing using optically tightly coupled FPGAs. JOCN 14(2): A166-A179 (2022) - [j50]Yoshiya Shikama, Ryuta Kawano, Hiroki Matsutani, Hideharu Amano, Yusuke Nagasaka, Naoto Fukumoto, Michihiro Koibuchi:
A traffic-aware memory-cube network using bypassing. Microprocess. Microsystems 90: 104471 (2022) - [c125]Yutaka Urino, Takanori Shimizu, Hiroshi Yamaguchi, Kenji Mizutani, Shigeru Nakamura, Tatsuya Usuki, Michihiro Koibuchi:
A Scalable Distributed Radix Sorter for FPGA Clusters using High-Bandwidth Memory Networks. FCCM 2022: 1 - [c124]Ryuta Kawano, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
Dynamic Routing Reconfiguration for Low-Latency and Deadlock-Free Interconnection Networks. CANDAR 2022: 117-123 - [c123]Jacir Luiz Bordim, Michihiro Koibuchi, Satoshi Fujita, Koji Nakano:
Message from the Organizers: CANDAR 2022. CANDAR 2022: viii - [c122]Kien Trung Pham, Truong Thao Nguyen, Hiroshi Yamaguchi, Yutaka Urino, Michihiro Koibuchi:
Scalable Low-Latency Inter-FPGA Networks. IPDPS 2022: 234-245 - [c121]Yoshiya Shikama, Michihiro Koibuchi, Hideharu Amano:
A Hardware Trojan Exploiting Coherence Protocol on NoCs. PDCAT 2022: 301-313 - [c120]Ke Cui, Michihiro Koibuchi:
A High-Radix Circulant Network Topology for Efficient Collective Communication. PDCAT 2022: 401-412 - 2021
- [j49]Kohei Ito, Kensuke Iizuka, Kazuei Hironaka, Yao Hu, Michihiro Koibuchi, Hideharu Amano:
Improving the Performance of Circuit-Switched Interconnection Network for a Multi-FPGA System. IEICE Trans. Inf. Syst. 104-D(12): 2029-2039 (2021) - [j48]Tomoya Itsubo, Michihiro Koibuchi, Hideharu Amano, Hiroki Matsutani:
An FPGA-Based Optimizer Design for Distributed Deep Learning with Multiple GPUs. IEICE Trans. Inf. Syst. 104-D(12): 2057-2067 (2021) - [j47]Kenji Mizutani, Hiroshi Yamaguchi, Yutaka Urino, Michihiro Koibuchi:
OPTWEB: A Lightweight Fully Connected Inter-FPGA Network for Efficient Collectives. IEEE Trans. Computers 70(6): 849-862 (2021) - [c119]Ryuta Kawano, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
GPU Parallelization of All-Pairs-Shortest-Path Algorithm in Low-Degree Unweighted Regular Graph. ACIT 2021: 51-55 - [c118]Shoichi Hirasawa, Hayato Yamaki, Michihiro Koibuchi:
Packet Forwarding Cache of Commodity Switches for Parallel Computers. CLUSTER 2021: 366-376 - [c117]Naoya Niwa, Hideharu Amano, Michihiro Koibuchi:
Low-Latency High-Bandwidth Interconnection Networks by Selective Packet Compression. CANDAR 2021: 56-64 - [c116]Yao Hu, Michihiro Koibuchi:
The Case for Disjoint Job Mapping on High-Radix Networked Parallel Computers. ICA3PP (2) 2021: 123-143 - [c115]Yao Hu, Michihiro Koibuchi:
Accelerating MPI Communication Using Floating-point Compression on Lossy Interconnection Networks. LCN 2021: 355-358 - [c114]Kenji Mizutani, Hiroshi Yamaguchi, Yutaka Urino, Michihiro Koibuchi:
Accelerating Parallel Sort on Tightly-Coupled FPGAs enabled by Onboard Si-Photonics Transceivers. OFC 2021: 1-3 - [c113]Naoya Niwa, Yoshiya Shikama, Hideharu Amano, Michihiro Koibuchi:
A Case for Low-Latency Network-on-Chip using Compression Routers. PDP 2021: 134-142 - [c112]Yoshiya Shikama, Ryuta Kawano, Hiroki Matsutani, Hideharu Amano, Yusuke Nagasaka, Naoto Fukumoto, Michihiro Koibuchi:
Low-Latency Low-Energy Memory-Cube Networks using Dual-Voltage Datapaths. PDP 2021: 143-147 - 2020
- [j46]Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
A Generalized Theory Based on the Turn Model for Deadlock-Free Irregular Networks. IEICE Trans. Inf. Syst. 103-D(1): 101-110 (2020) - [j45]Ke Cui, Michihiro Koibuchi:
Efficient Two-Opt Collective-Communication Operations on Low-Latency Random Network Topologies. IEICE Trans. Inf. Syst. 103-D(12): 2435-2443 (2020) - [j44]Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
Traffic-Independent Multi-Path Routing for High-Throughput Data Center Networks. IEICE Trans. Inf. Syst. 103-D(12): 2471-2479 (2020) - [j43]Yao Hu, Michihiro Koibuchi:
Application Mapping and Scheduling of Uncertain Communication Patterns onto Non-Random and Random Network Topologies. IEICE Trans. Inf. Syst. 103-D(12): 2480-2493 (2020) - [c111]Takeo Hosomi, Ryota Yasudo, Michihiro Koibuchi, Shinji Shimojo:
Dual-Plane Isomorphic Hypercube Network. HPC Asia 2020: 73-80 - [c110]Kohei Ito, Kensuke Iizuka, Kazuei Hironaka, Yao Hu, Michihiro Koibuchi, Hideharu Amano:
Implementing a Multi-ejection Switch and Making the Use of Multiple Lanes in a Circuit-switched Multi-FPGA System. CANDAR (Workshops) 2020: 211-217 - [c109]Ke Cui, Michihiro Koibuchi:
A Diagonal Checksum Algorithm-Based Fault Tolerance for Parallel Matrix Multiplication. CANDAR (Workshops) 2020: 218-223 - [c108]Tomoya Itsubo, Michihiro Koibuchi, Hideharu Amano, Hiroki Matsutani:
Accelerating Deep Learning using Multiple GPUs and FPGA-Based 10GbE Switch. PDP 2020: 102-109
2010 – 2019
- 2019
- [j42]Yao Hu, Michihiro Koibuchi:
Optimizing Slot Utilization and Network Topology for Communication Pattern on Circuit-Switched Parallel Computing Systems. IEICE Trans. Inf. Syst. 102-D(2): 247-260 (2019) - [j41]Michihiro Koibuchi:
Foreword. IEICE Trans. Inf. Syst. 102-D(12): 2280 (2019) - [j40]Ryota Yasudo, Michihiro Koibuchi, Koji Nakano, Hiroki Matsutani, Hideharu Amano:
Designing High-Performance Interconnection Networks with Host-Switch Graphs. IEEE Trans. Parallel Distributed Syst. 30(2): 315-330 (2019) - [c107]Michihiro Koibuchi, Lambert T. Leong, Tomohiro Totoki, Naoya Niwa, Hiroki Matsutani, Hideharu Amano, Henri Casanova:
Sparse 3-D NoCs with Inductive Coupling. DAC 2019: 49 - [c106]Yao Hu, Michihiro Koibuchi:
Diameter/ASPL-Based Mapping of Applications with Uncertain Communication over Random Interconnection Networks. ICPADS 2019: 249-258 - [c105]Michihiro Koibuchi, Ikki Fujiwara, Naoya Niwa, Tomohiro Totoki, Shoichi Hirasawa:
The Case for Water-Immersion Computer Boards. ICPP 2019: 29:1-29:10 - [c104]Yao Hu, Michihiro Koibuchi:
The Impact of Application Mapping on Non-Random and Random Network Topologies. ISPA/BDCloud/SocialCom/SustainCom 2019: 16-25 - [c103]Keita Azegami, Kazusa Musha, Kazuei Hironaka, Akram Ben Ahmed, Michihiro Koibuchi, Yao Hu, Hideharu Amano:
A STDM (Static Time Division Multiplexing) Switch on a Multi-FPGA System. MCSoC 2019: 328-333 - [c102]Michihiro Koibuchi:
Low-Latency Error-Prone Optical Networks for Fast Approximate Computation on High-End Datacenters. OECC/PSC 2019: 1-2 - 2018
- [j39]Koya Mitsuzuka, Michihiro Koibuchi, Hideharu Amano, Hiroki Matsutani:
Proxy Responses by FPGA-Based Switch for MapReduce Stragglers. IEICE Trans. Inf. Syst. 101-D(9): 2258-2268 (2018) - [j38]Yao Hu, Michihiro Koibuchi:
Enhancing Job Scheduling on Inter-Rackscale Datacenters with Free-Space Optical Links. IEICE Trans. Inf. Syst. 101-D(12): 2922-2932 (2018) - [c101]Yao Hu, Michihiro Koibuchi:
The Impact of Job Mapping on Random Network Topology. CANDAR Workshops 2018: 79-85 - [c100]Ke Cui, Michihiro Koibuchi:
Performance Evaluation of Collective Communication on Random Network Topology. CANDAR Workshops 2018: 159-162 - [c99]Naoya Niwa, Tomohiro Totoki, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
An Trace-Driven Performance Prediction Method for Exploring NoC Design Optimization. CANDAR Workshops 2018: 182-185 - [c98]Tomohiro Totoki, Michihiro Koibuchi, Hideharu Amano:
An Extension of A Temperature Modeling Tool HotSpot 6.0 for Castle-of-Chips Stacking. CANDAR Workshops 2018: 363-369 - [c97]Akram Ben Ahmed, Hayate Okuhara, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
Adaptive Body Bias Control Scheme for Ultra Low-Power Network-on-Chip Systems. MCSoC 2018: 146-153 - [c96]Truong Thao Nguyen, Hiroki Matsutani, Michihiro Koibuchi:
Low-Reliable Low-Latency Networks Optimized for HPC Parallel Applications. NCA 2018: 1-10 - [c95]Akram Ben Ahmed, Daichi Fujiki, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
AxNoC: Low-power Approximate Network-on-Chips using Critical-Path Isolation. NOCS 2018: 6:1-6:8 - 2017
- [j37]Ryuta Kawano, Hiroshi Nakahara, Seiichi Tade, Ikki Fujiwara, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
A Novel Channel Assignment Method to Ensure Deadlock-Freedom for Deterministic Routing. IEICE Trans. Inf. Syst. 100-D(8): 1798-1806 (2017) - [j36]Ryuta Kawano, Hiroshi Nakahara, Ikki Fujiwara, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
A Layout-Oriented Routing Method for Low-Latency HPC Networks. IEICE Trans. Inf. Syst. 100-D(12): 2796-2807 (2017) - [j35]Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tadao Nakamura:
Scalable Networks-on-Chip with Elastic Links Demarcated by Decentralized Routers. IEEE Trans. Computers 66(4): 702-716 (2017) - [j34]Nguyen T. Truong, Ikki Fujiwara, Michihiro Koibuchi, Khanh-Van Nguyen:
Distributed Shortcut Networks: Low-Latency Low-Degree Non-Random Topologies Targeting the Diameter and Cable Length Trade-Off. IEEE Trans. Parallel Distributed Syst. 28(4): 989-1001 (2017) - [c94]Thao-Nguyen Nguyen, Michihiro Koibuchi:
Cable-geometric error-prone approach for low-latency interconnection networks. CCGrid 2017: 699-702 - [c93]Michihiro Koibuchi, Tomohiro Totoki, Hiroki Matsutani, Hideharu Amano, Fabien Chaix, Ikki Fujiwara, Henri Casanova:
A Case for Uni-directional Network Topologies in Large-Scale Clusters. CLUSTER 2017: 178-187 - [c92]Koya Mitsuzuka, Ami Hayashi, Michihiro Koibuchi, Hideharu Amano, Hiroki Matsutani:
In-switch approximate processing: Delayed tasks management for MapReduce applications. FPL 2017: 1-4 - [c91]Daichi Fujiki, Kiyo Ishii, Ikki Fujiwara, Hiroki Matsutani, Hideharu Amano, Henri Casanova, Michihiro Koibuchi:
High-Bandwidth Low-Latency Approximate Interconnection Networks. HPCA 2017: 469-480 - [c90]Takashi Kurimoto, Shigeo Urushidani, Hiroshi Yamada, Kenjiro Yamanaka, Motonori Nakamura, Shunji Abe, Kensuke Fukuda, Michihiro Koibuchi, Hiroki Takakura, Shigeki Yamada, Yusheng Ji:
SINET5: A low-latency and high-bandwidth backbone network for SDN/NFV Era. ICC 2017: 1-7 - [c89]Yao Hu, Hiroaki Hara, Ikki Fujiwara, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi:
Towards Tightly-coupled Datacenter with Free-space Optical Links. ICCBDC 2017: 33-39 - [c88]Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
HiRy: An Advanced Theory on Design of Deadlock-Free Adaptive Routing for Arbitrary Topologies. ICPADS 2017: 664-673 - [c87]Ryota Yasudo, Michihiro Koibuchi, Koji Nakano, Hiroki Matsutani, Hideharu Amano:
Order/Radix Problem: Towards Low End-to-End Latency Interconnection Networks. ICPP 2017: 322-331 - [c86]Hiroshi Nakahara, Ryota Yasudo, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi:
3D Layout of Spidergon, Flattened Butterfly and Dragonfly on a Chip Stack with Inductive Coupling Through Chip Interface. ISPAN-FCST-ISCC 2017: 52-59 - [c85]Yao Hu, Tomohiro Kudoh, Michihiro Koibuchi:
A Case of Electrical Circuit Switched Interconnection Network for Parallel Computers. PDCAT 2017: 276-283 - 2016
- [j33]Michihiro Koibuchi, Ikki Fujiwara, Kiyo Ishii, Shu Namiki, Fabien Chaix, Hiroki Matsutani, Hideharu Amano, Tomohiro Kudoh:
Optical network technologies for HPC: computer-architects point of view. IEICE Electron. Express 13(6): 20152007 (2016) - [j32]Truong Thao Nguyen, Khanh-Van Nguyen, Ikki Fujiwara, Michihiro Koibuchi:
Layout-Conscious Expandable Topology for Low-Degree Interconnection Networks. IEICE Trans. Inf. Syst. 99-D(5): 1275-1284 (2016) - [j31]Akram Ben Ahmed, Hiroki Matsutani, Michihiro Koibuchi, Kimiyoshi Usami, Hideharu Amano:
Multi-Voltage Variable Pipeline Routers with the Same Clock Frequency for Low-Power Network-on-Chips Systems. IEICE Trans. Electron. 99-C(8): 909-917 (2016) - [j30]Yao Hu, Ikki Fujiwara, Michihiro Koibuchi:
Job Mapping and Scheduling on Free-Space Optical Networks. IEICE Trans. Inf. Syst. 99-D(11): 2694-2704 (2016) - [j29]Hiroshi Nakahara, Tomoya Ozaki, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
Novel Chip Stacking Methods to Extend Both Horizontally and Vertically for Many-Core Architectures with ThrouChip Interface. IEICE Trans. Inf. Syst. 99-D(12): 2871-2880 (2016) - [j28]Takahiro Kagami, Hiroki Matsutani, Michihiro Koibuchi, Yasuhiro Take, Tadahiro Kuroda, Hideharu Amano:
Efficient 3-D Bus Architectures for Inductive-Coupling ThruChip Interfaces. IEEE Trans. Very Large Scale Integr. Syst. 24(2): 493-506 (2016) - [c84]Ryuta Kawano, Hiroshi Nakahara, Seiichi Tade, Ikki Fujiwara, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
ACRO: Assignment of channels in reverse order to make arbitrary routing deadlock-free. ICIS 2016: 1-6 - [c83]Yao Hu, Ikki Fujiwara, Michihiro Koibuchi:
HPC Job Mapping over Reconfigurable Wireless Links. CCGrid 2016: 570-575 - [c82]Ryuta Kawano, Hiroshi Nakahara, Ikki Fujiwara, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
LOREN: A Scalable Routing Method for Layout-Conscious Random Topologies. CANDAR 2016: 9-18 - [c81]Michihiro Koibuchi, Ikki Fujiwara, Fabien Chaix, Henri Casanova:
Towards Ideal Hop Counts in Interconnection Networks with Arbitrary Size. CANDAR 2016: 188-194 - [c80]Thanh-Chung Kieu, Khanh-Van Nguyen, Nguyen T. Truong, Ikki Fujiwara, Michihiro Koibuchi:
An Interconnection Network Exploiting Trade-Off between Routing Table Size and Path Length. CANDAR 2016: 666-670 - [c79]Satoshi Fujita, Koji Nakano, Michihiro Koibuchi, Ikki Fujiwara:
Deterministic Construction of Regular Geometric Graphs with Short Average Distance and Limited Edge Length. ICA3PP 2016: 295-309 - [c78]Koji Nakano, Daisuke Takafuji, Satoshi Fujita, Hiroki Matsutani, Ikki Fujiwara, Michihiro Koibuchi:
Randomly Optimized Grid Graph for Low-Latency Interconnection Networks. ICPP 2016: 340-349 - [c77]Takashi Kurimoto, Shigeo Urushidani, Hiroshi Yamada, Kenjiro Yamanaka, Motonori Nakamura, Shunji Abe, Kensuke Fukuda, Michihiro Koibuchi, Yusheng Ji, Hiroki Takakura, Shigeki Yamada:
A fully meshed backbone network for data-intensive sciences and SDN services. ICUFN 2016: 909-911 - [c76]Daichi Fujiki, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
Randomizing Packet Memory Networks for Low-Latency Processor-Memory Communication. PDP 2016: 168-175 - [c75]Fabien Chaix, Ikki Fujiwara, Michihiro Koibuchi:
Suitability of the Random Topology for HPC Applications. PDP 2016: 301-304 - [c74]Truong Thao Nguyen, Ikki Fujiwara, Michihiro Koibuchi:
A diagonal cabling approach to data center and HPC systems. SoICT 2016: 265-271 - 2015
- [j27]Shigeo Urushidani, Shunji Abe, Kenjiro Yamanaka, Kento Aida, Shigetoshi Yokoyama, Hiroshi Yamada, Motonori Nakamura, Kensuke Fukuda, Michihiro Koibuchi, Shigeki Yamada:
New Directions for a Japanese Academic Backbone Network. IEICE Trans. Inf. Syst. 98-D(3): 546-556 (2015) - [j26]Ahmed Shalaby, Ikki Fujiwara, Michihiro Koibuchi:
The Case for Network Coding for Collective Communication on HPC Interconnection Networks. IEICE Trans. Inf. Syst. 98-D(3): 661-670 (2015) - [j25]Ikki Fujiwara, Michihiro Koibuchi, Hiroki Matsutani, Henri Casanova:
Swap-And-Randomize: A Method for Building Low-Latency HPC Interconnects. IEEE Trans. Parallel Distributed Syst. 26(7): 2051-2060 (2015) - [c73]Seiichi Tade, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi:
A metamorphotic Network-on-Chip for various types of parallel applications. ASAP 2015: 98-105 - [c72]Ikki Fujiwara, Michihiro Koibuchi, Tomoya Ozaki, Hiroki Matsutani, Henri Casanova:
Augmenting low-latency HPC network with free-space optical links. HPCA 2015: 390-401 - [c71]Yao Hu, Ikki Fujiwara, Michihiro Koibuchi:
Enabling Ideal Job Mapping on Wireless Supercomputers and Datacenters. CANDAR 2015: 357-363 - [c70]Hiroshi Nakahara, Tomoya Ozaki, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
Expandable Chip Stacking Method for Many-core Architectures Consisting of Tiny Chips. MCSoC 2015: 41-48 - [c69]Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tadao Nakamura:
On-Chip Decentralized Routers with Balanced Pipelines for Avoiding Interconnect Bottleneck. NOCS 2015: 16:1-16:8 - [c68]Ryuta Kawano, Seiichi Tade, Ikki Fujiwara, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi:
Optimized Core-Links for Low-Latency NoCs. PDP 2015: 172-176 - [c67]Michihiro Koibuchi:
Singularity of Future Computer-System Networks. SoICT 2015: 3 - 2014
- [j24]Hao Zhang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
Dynamic Power Consumption Optimization for Inductive-Coupling based Wireless 3D NoCs. IPSJ Trans. Syst. LSI Des. Methodol. 7: 27-36 (2014) - [j23]Satoshi Matsuoka, Hitoshi Sato, Osamu Tatebe, Michihiro Koibuchi, Ikki Fujiwara, Shuji Suzuki, Masanori Kakuta, Takashi Ishida, Yutaka Akiyama, Toyotaro Suzumura, Koji Ueno, Hiroki Kanezashi, Takemasa Miyoshi:
Extreme Big Data (EBD): Next Generation Big Data Infrastructure Technologies Towards Yottabyte/Year. Supercomput. Front. Innov. 1(2): 89-107 (2014) - [j22]Yasuhiro Take, Hiroki Matsutani, Daisuke Sasaki, Michihiro Koibuchi, Tadahiro Kuroda, Hideharu Amano:
3D NoC with Inductive-Coupling Links for Building-Block SiPs. IEEE Trans. Computers 63(3): 748-763 (2014) - [j21]Shigeo Urushidani, Michihiro Aoki, Kensuke Fukuda, Shunji Abe, Motonori Nakamura, Michihiro Koibuchi, Yusheng Ji, Shigeki Yamada:
Highly available network design and resource management of SINET4. Telecommun. Syst. 56(1): 33-47 (2014) - [c66]Hiroki Matsutani, Michihiro Koibuchi, Ikki Fujiwara, Takahiro Kagami, Yasuhiro Take, Tadahiro Kuroda, Paul Bogdan, Radu Marculescu, Hideharu Amano:
Low-latency wireless 3D NoCs via randomized shortcut chips. DATE 2014: 1-6 - [c65]Fabien Chaix, Ikki Fujiwara, Michihiro Koibuchi:
Darkfiber Planning for Extensible HPC Network Design under Uncertainties. CANDAR 2014: 382-387 - [c64]Nguyen T. Truong, Van K. Nguyen, Nhat T. X. Le, Ikki Fujiwara, Fabien Chaix, Michihiro Koibuchi:
Layout-aware expandable low-degree topology. ICPADS 2014: 462-470 - [c63]Ikki Fujiwara, Michihiro Koibuchi, Hiroki Matsutani, Henri Casanova:
Skywalk: A Topology for HPC Networks with Low-Delay Switches. IPDPS 2014: 263-272 - [c62]Ahmed Shalaby, Mohamed El-Sayed Ragab, Victor Goulart, Ikki Fujiwara, Michihiro Koibuchi:
Hierarchical Network Coding for Collective Communication on HPC Interconnects. PDP 2014: 98-102 - 2013
- [j20]Cisse Ahmadou Dit Adi, Michihiro Koibuchi, Masato Yoshimi, Hidetsugu Irie, Tsutomu Yoshinaga:
A Fully Optical Ring Network-on-Chip with Static and Dynamic Wavelength Allocation. IEICE Trans. Inf. Syst. 96-D(12): 2545-2554 (2013) - [c61]Hiroki Matsutani, Paul Bogdan, Radu Marculescu, Yasuhiro Take, Daisuke Sasaki, Hao Zhang, Michihiro Koibuchi, Tadahiro Kuroda, Hideharu Amano:
A case for wireless 3D NoCs for CMPs. ASP-DAC 2013: 23-28 - [c60]