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ORCIDNORCHIP 2012: Copenhagen, Denmark
- NORCHIP 2012, Copenhagen, Denmark, November 12-13, 2012. IEEE 2012, ISBN 978-1-4673-2221-8
- Jonas Stenbaek Hegner, Joakim Sindholt, Alberto Nannarelli
:
Design of power efficient FPGA based hardware accelerators for financial applications. 1-4 - S. Balasubramanian, Waleed Khalil:
Architectural trends in GHz speed DACs. 1-4 - Shanthi Sudalaiyandi, Tor Sverre Lande:
A continuous-time IR-UWB RAKE receiver for coherent symbol detection. 1-4 - Jia Mao, Zhuo Zou, David Sarmiento M., Fredrik Jonsson, Li-Rong Zheng:
A power scalable and high pulse swing UWB transmitter for wirelessly-powered RFID applications. 1-4 - Kristian Gjertsen Kjelgård, Tor Sverre Lande:
A 26 GHz UWB CMOS IR-UWB transmitter with on-chip balun. 1-4 - Iracu O. Santos, Alba Sandyra Bezerra Lopes, Bruno M. Carvalho, Edgard de Faria Corrêa, Márcio Eduardo Kreutz:
H.264/AVC motion estimation on FPGAs and GPUs: A comparative study. 1-4 - Peteris Misans, Uldis Derums, Vents Kanders:
FPGA implementation of elementary generalized unitary rotation with CORDIC based architecture. 1-6 - Chenxin Zhang, Hemanth Prabhu, Liang Liu, Ove Edfors, Viktor Öwall:
Energy efficient MIMO channel pre-processor using a low complexity on-line update scheme. 1-4 - Eirik Steen-Hansen, Trond Ytterdal:
Modeling and design of a dual-residue pipelined ADC in 130nm CMOS. 1-4 - Tuan Vu Cao, Snorre Aunet, Trond Ytterdal:
A 9-bit 50MS/s asynchronous SAR ADC in 28nm CMOS. 1-6 - Lucas Machado, Mayler G. A. Martins, Vinicius Callegaro, Renato P. Ribas, André Inácio Reis:
KL-cut based digital circuit remapping. 1-4 - Mark Ruvald Pedersen, Jan Madsen:
Optimal register allocation by augmented left-edge algorithm on arbitrary control-flow structures. 1-6 - Shailesh Singh Chouhan, Kari Halonen:
A Novel on-chip ultra-low power temperature sensing scheme. 1-4 - Francesca Cucchi, Stefano Di Pascoli, Giuseppe Iannaccone:
Variability-aware design of 55 nA current reference with 1.4% standard deviation and 290 nW power consumption. 1-4 - Wolfgang Gut, Gerald Hilber, Dominik Gruber, Manuel Kaufmann, Andreas Rauchenecker, Timm Ostermann:
Low power Real Time Clock with high accuracy over large supply voltage range. 1-4 - Iason Filippopoulos, Francky Catthoor, Per Gunnar Kjeldsberg, Elena Hammari, Jos Huisken:
Memory-aware system scenario approach energy impact. 1-6 - Vahid Saljooghi, Alen Bardizbanyan, Magnus Själander, Per Larsson-Edefors:
Configurable RTL model for level-1 caches. 1-4 - Azam Seyedi, Adrià Armejach, Adrián Cristal, Osman S. Unsal, Mateo Valero:
Novel SRAM bias control circuits for a low power L1 data cache. 1-6 - Sima Payami, Amin Ojani:
An operational amplifier for high performance pipelined ADCs in 65nm CMOS. 1-4 - Vladimir M. Milovanovic, Horst Zimmermann:
Analyses of single-stage complementary self-biased CMOS differential amplifiers. 1-4 - Mehran Baboli, Olga Boric-Lubecke, Victor Lubecke:
Heart and respiratory detection and simulations for tracking humans based on respiration by using pulse-based radar. 1-4 - Maris Terauds:
Implementation of FPGA based DSP module for CW Doppler radar: Preliminary results. 1-6 - Ali Fazli Yeknami, Atila Alvandpour:
A 2.1 µW 76 dB SNDR DT-ΔΣ modulator for medical implant devices. 1-4 - Nadeem Afzal, J. Jacob Wikner:
Power efficient arrangement of oversampling sigma-delta DAC. 1-4 - Ping Lu, Pietro Andreani, Antonio Liscidini:
A 90nm CMOS gated-ring-oscillator-based 2-dimension Vernier time-to-digital converter. 1-4 - Joakim Alvbrant, J. Jacob Wikner:
Study and simulation of an example redundant FIR filter. 1-4 - Nowshad Painda Mand, Francesco Robino, Johnny Öberg:
Artificial neural network emulation on NOC based multi-core FPGA platform. 1-4 - Deena M. Zamzam, Mohamed A. Abd El-Ghany, Klaus Hofmann:
Performability of error control schemes for NOC interconnects. 1-5 - Felice Francesco Tafuri, Cataldo Guaragnella, Marco Fiore, Torben Larsen:
Linearization of RF power amplifiers using an enhanced memory polynomial predistorter. 1-4 - Wei Wei, Jan H. Mikkelsen, Ole Kiel Jensen:
Deembedding static nonlinearities of power amplifiers using least square error algorithm. 1-4 - Imad ud Din, Johan Wernehag, Stefan Back Andersson, Sven Mattisson:
Wideband Reconfigurable Capacitive shunt-feedback LNA in 65nm CMOS. 1-4 - Mitesh Yogesh, Puneet Sareen, Markus Dietl, Ketan Dewan:
A 2.5 GHz self-compensated, bandwidth tracking PLL with 0.8 ps jitter. 1-4 - Saif Uddin, Johnny Öberg:
Testing of an off-chip NoC protocol using a BIST/Synthesizable Testbench approach. 1-5 - Rasmus Bo Sørensen, Martin Schoeberl, Jens Sparsø:
A light-weight statically scheduled network-on-chip. 1-6 - Ahmed Shalaby, Mohamed El-Sayed Ragab, Victor Goulart:
Intermediate nodes selection schemes for Network Coding in Network-on-Chips. 1-5 - Haoyuan Ying, Kris Heid, Thomas Hollstein, Klaus Hofmann:
A genetic algorithm based optimization method for low vertical link density 3-dimensional Networks-on-Chip many core systems. 1-4 - Dag T. Wisland:
Nanoscale CMOS impulse radar - from research to product. 1 - Ivan H. H. Jørgensen:
Challenges in IC design for hearing aids. 1 - Hanspeter Schmid:
Electrical and human feedback. 1-10 - Jan Madsen:
Biochips: The integrated circuit of biology. 1 - Jia Sun, Timo Rahkonen, Marko Neitola:
Behavioral modeling of nonlinear settling for multiple cascaded SC stages. 1-6 - Prakash Harikumar, Muhammad Irfan Kazim, J. Jacob Wikner:
An analog receiver front-end for capacitive body-coupled communication. 1-4 - Daniel Svard, Christer Jansson, Atila Alvandpour:
A readout circuit for an uncooled IR camera with mismatch and self-heating compensation. 1-4 - Oliver Schrape, Frank Vater:
Embedded low power clock generator for sensor nodes. 1-4 - Quoc-Tai Duong, Jerzy J. Dabrowski:
Wideband RF detector design for high performance on-chip test. 1-4 - Elias Bakken, Tor Sverre Lande, Sverre Holm:
Effect of process variations in CMOS chips for radar beamforming. 1-4 - Stefan Hauser, Nico Moser, Ben H. H. Juurlink:
SynZEN: A hybrid TTA/VLIW architecture with a distributed register file. 1-4 - Fatemeh Khalili, Hamid R. Zarandi:
A fault-aware low-energy spare core allocation in networks-on-chip. 1-4 - Jing Zhou, Zengrong Liu, Lei Chen, Shuo Wang, Zhiping Wen, Xun Chen, Chang Qi:
An accurate fault location method based on configuration bitstream analysis. 1-5 - Vinícius Dal Bem, André Inácio Reis, Renato P. Ribas:
Lithography analysis of via-configurable transistor-array fabrics. 1-4 - Srinivasa Reddy Kuppireddi, Sayanu Pamidighantam, V. Janardhana, Oddvar Søråsen, J. S. Roy, R. G. Kulkarn:
Evaluation of SU8 photo polymer for microwave packaging applications. 1-4 - Andrea Simonetti:
A measurement technique for the vibrating wire sensors. 1-6 - Raimund Ubar, Viljar Indus, Oliver Kalmend, Teet Evartson, Elmet Orasson:
Functional Built-In Self-Test for processor cores in SoC. 1-4 - Behrad Niazmand, Midia Reshadi, Akram Reza:
PathAware: A contention-aware selection function for application-specific Network-On-Chips. 1-6 - Dipak S. Marathe:
A survey on mixed operating mode/self synchronization. 1-3 - Lauri Matilainen, Sakari Lahti, Otto Esko, Erno Salminen, Timo D. Hämäläinen:
Integration of TTA processor tools to Kactus2 IP-XACT design flow. 1-6
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