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ORCIDReCoSoC 2007: Montpellier, France
- Gilles Sassatelli, Manfred Glesner, Christophe Bobda, Pascal Benoit:
Proceedings of the 3rd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, ReCoSoC 2007, Montpellier, France, June 2007. Univ. Montpellier II 2007, ISBN 2-9517461-3-X
Session 1. Low Power / Ansynchronous ReCoSoC Platforms
- Katarina Paulsson, Michael Hübner, Salih Bayar, Jürgen Becker:
Exploitation of Run-Time Partial Reconfiguration for Dynamic Power Management in Xilinx Spartan III-based Systems. ReCoSoC 2007: 1-6 - Tudor Murgan, Andre Guntoro, Heiko Hinkelmann, Petru Bogdan Bacinschi, Manfred Glesner:
Low-Complexity Adaptive Encoding Schemes Based on Partial Bus-Invert for Power Reduction in Buses Exhibiting Capacitive Coupling. ReCoSoC 2007: 7-14 - Philippe Hoogvorst, Sylvain Guilley, Sumanta Chaudhuri, Alin Razafindraibe, Taha Beyrouthy, Laurent Fesquet:
A Reconfigurable Cell for a Multi-Style Asynchronous FPGA. ReCoSoC 2007: 15-22
Session 2. Self-Adaptive Systems
- Leandro Möller, Ismael Grehs, Ewerson Carvalho, Rafael Soares, Ney Calazans, Fernando Moraes:
A NoC-based Infrastructure to Enable Dynamic Self Reconfigurable Systems. ReCoSoC 2007: 23-30 - Marcelo Götz, Tao Xie, Florian Dittmann:
Dynamic Relocation of Hybrid Tasks: A Complete Design Flow. ReCoSoC 2007: 31-38 - Nicolas Saint-Jean, Camille Jalier, Gilles Sassatelli, Pascal Benoit, Lionel Torres, Michel Robert:
HS Scale: A run-time adaptable MP-SoC architecture. ReCoSoC 2007: 39-46 - Kurt Franz Ackermann, Leandro Soares Indrusiak, Manfred Glesner:
System Level Design of a Dynamically Self-Reconfigurable Image Processing System. ReCoSoC 2007: 47-54
Session 3. Processors and Multiprocessors in Embedded Systems
- Peter Zipf, Heiko Hinkelmann, Felix Missel, Manfred Glesner:
A Customizable LEON2-Based VLIW Processor. ReCoSoC 2007: 55-60 - Hritam Dutta, Frank Hannig, Alexey Kupriyanov, Dmitrij Kissler, Jürgen Teich, Rainer Schaffer, Sebastian Siegel, Renate Merker, Bernard Pottier:
Massively Parallel Processor Architectures: A Co-design Approach. ReCoSoC 2007: 61-68 - Mehdi Jallouli, Camille Diou, Fabrice Monteiro:
Stack processor architecture and development methods suitable for dependable applications. ReCoSoC 2007: 69-75
Session 4. Mapping and Programming Models
- Samar Yazdani, Joel Cambonie, Bernard Pottier:
Coordinated concurrent memory accesses on a reconfigurable multimedia processor. ReCoSoC 2007: 76-83 - Sanna Määttä, Jari Nurmi:
Experiences of Using Object Oriented Programming Methods in High Level Network-on-Chip and System-on-Chip Design. ReCoSoC 2007: 84-89 - Sébastien Le Beux, Philippe Marquet, Jean-Luc Dekeyser:
Multiple Abstraction Views of FPGA to Map Parallel Applications. ReCoSoC 2007: 90-97
Session 5. NOC Architectures
- Slavisa Jovanovic, Camel Tanougast, Christophe Bobda, Serge Weber:
A Dynamic Communication Structure for Dynamically Reconfigurable FPGAs. ReCoSoC 2007: 98-105 - Thomas Haller, Christophe Bobda:
Adaptive Network for Multiprocessing in Programmable Logic Devices. ReCoSoC 2007: 106-110 - Antoine Scherrer, Antoine Fraboulet, Tanguy Risset:
Long-Range Dependence and On-chip Processor Traffic. ReCoSoC 2007: 111-120
Session 6. Test and Verification in ReCoSoC Platforms
- Brendan Mullane, Chen-Huan Chiang, Michael Higgins, Ciaran MacNamee, Tapan J. Chakraborty, Thomas B. Cook:
FPGA Prototyping of a Scan Based System-On-Chip Design. ReCoSoC 2007: 121-126 - Anatol Ursu:
Latch Inference for Equivalence Checking. ReCoSoC 2007: 127-131
Session 7. Security Issues in ReCoSoC Platforms
- Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre:
A Dependable Parallel Architecture for SBoxes. ReCoSoC 2007: 132-137 - Eduardo Braulio Wanderley Netto, Reouven Elbaz, Lionel Torres, Gilles Sassatelli, Romain Vaslin, Guy Gogniat, Jean-Philippe Diguet:
IBC-EI: An Instruction Based Compression method with Encryption and Integrity Checking. ReCoSoC 2007: 138-145 - Romain Vaslin, Guy Gogniat, Eduardo Braulio Wanderley Netto, Russell Tessier, Wayne P. Burleson:
Low latency Solution for Confidentiality and Integrity Checking in Embedded Systems with Off-Chip Memory. ReCoSoC 2007: 146-153 - Alberto Ferrante, Antonio Vincenzo Taddeo, Mariagiovanna Sami, Fabrizio Mantovani, Jurijs Fridkins:
Self-adaptive Security at Application Level: a Proposal. ReCoSoC 2007: 154-160
Session 8. Applications in ReCoSoC Systems
- Hervé Berviller, Vincent Frick, Philippe Bougeot, Jean-Philippe Blonde, Julien Oster, Jacques Felblinger:
FPGA Implemenatation of an Adaptive Filtering: Application on ECG Signal Artefact Suppression in MRI Environment. ReCoSoC 2007: 161-165 - Fabio Garzia, Claudio Brunelli, Andrea Ferro, Jari Nurmi:
Implementation of a 2D low-pass image filtering algorithm on a reconfigurable device. ReCoSoC 2007: 166-170 - Jose Alberto Vite-Frias, René de Jesús Romero-Troncoso, Alejandro Ordaz-Moreno, Jesus Rooney Rivera-Guillen, Arturo Garcia-Perez:
Special Purpose Multi-processor for On-line Fault Detection on Induction Motors during Steady State. ReCoSoC 2007: 171-176
Session 9. Design of Reconfigurable Architectures
- Junchen Liu, Ian O'Connor, David Navarro, Frédéric Gaffiot:
A Family of Ultra-Fine Grain CNTFET-based Reconfigurable Logic Gates. ReCoSoC 2007: 177-185 - Heiko Hinkelmann, Tudor Murgan, Guifang Liu, Peter Zipf, Manfred Glesner:
On the Design of a Reconfigurable Multiplier for Integer and Galois Field Multiplication. ReCoSoC 2007: 185-191
Posters and Interactive Presentations
- Thomas Haller, José Rodrigo Azambuja, Christophe Bobda:
Automatic Generation of Adaptive Multiprocessor Systems. ReCoSoC 2007: 192-193 - Jesus Rooney Rivera-Guillen, René de Jesús Romero-Troncoso, Alejandro Ordaz-Moreno, Jose Alberto Vite-Frias:
Dedicated Multiprocessing Unit for Polynomial Evaluation on FPGA in CNC Profile Generation. ReCoSoC 2007: 194-195 - Alejandro Ordaz-Moreno, René de Jesús Romero-Troncoso, Jose Alberto Vite-Frias, Jesus Rooney Rivera-Guillen, Arturo Garcia-Perez:
Dedicated Special Purpose Multiprocessor System for the Diagnostic of Rotor Bar Breakage on Induction Motors. ReCoSoC 2007: 196-197 - Wladyslaw Szczesniak:
Selecting the Optimal Number of Functional Units of Digital Real Time Systems. ReCoSoC 2007: 198-199
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