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ORCIDSBCCI 2007: Copacabana, Rio de Janeiro, Brazil
- Antonio Petraglia, Volnei A. Pedroni, Gert Cauwenberghs:
Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2007, Copacabana, Rio de Janeiro, Brazil, September 3-6, 2007. ACM 2007, ISBN 978-1-59593-816-9
Invited talks & tutorials
- M. Jamal Deen
:
Highly sensitive, low-cost integrated biosensors. 1 - Takayasu Sakurai:
Meeting with the forthcoming IC design. 2 - Mohammed Ismail:
WiMAX: a competing or complementary technology to 3G? 3 - Betty Prince:
Nanotechnology and emerging memories. 4 - Subhomoy Chattopadhyay:
Low power design techniques for nanometer design processes: 65 nm and smaller. 5 - Ahmed A. Youssef:
RF architectures in CMOS for the emerging wireless technologies: challenges and opportunities. 6 - Mohammed Ismail:
First-pass-silicon radio IPs for B3G wireless networks. 7 - Gustavo Liñán Cembrano:
Focal plane processors & pixel level processing: mimicking natural vision systems to solve image processing problems. 8 - Betty Prince:
Embedded non-volatile memories. 9
A/D and D/A converters
- Hugo Daniel Hernández, Wilhelmus A. M. Van Noije, Elkim Roa, João Navarro Jr.:
A small area 8bits 50MHz CMOS DAC for bluetooth transmitter. 10-15 - Jørgen Andreas Michaelsen, Dag T. Wisland:
Suppression of delta-sigma DAC quantisation noise by bandwidth adaptation. 16-20 - Antonio J. Ginés, Eduardo J. Peralías, Adoración Rueda:
Novel swapping technique for background calibration of capacitor mismatching in pipeline ADCS. 21-26 - A. A. Mariano, B. Boumballa, Dominique Dallet, Yann Deval, Jean-Baptiste Bégueret:
High-speed CMOS analog-to-digital converter for front-end receiver applications. 27-30
Analog circuits - part 1
- Peterson R. Agostinho, Sandro A. P. Haddad, Jader A. De Lima, Wouter A. Serdijn, Osamu Saotome:
A ultra low power CMOS pA/V transconductor and its application to wavelet filters. 31-35 - Filipe G. Ramos, Laercio Caldeira, Tales Cleber Pimenta:
A programmable voltage reference optimized for power management applications. 36-41 - Dalton M. Colombo, Gilson I. Wirth, Sergio Bampi:
Trim range limited by noise in bandgap voltage references. 42-47
Analog circuits - part 2
- Filipe Costa Beber Vieira, César Augusto Prior, Cesar Ramos Rodrigues, Leonardo Perin, João Baptista dos Santos Martins:
Current mode instrumentation amplifier with rail-to-rail input and output. 48-52 - Fernando de Souza Campos, Ognian Marinov, Naser Faramarzpour, Fayçal Saffih, M. Jamal Deen, Jacobus W. Swart:
A multisampling time-domain CMOS imager with synchronous readout circuit. 53-58 - Carlos Fernando Teodósio Soares, Antonio Petraglia:
A systematic method to approximate capacitance ratios to improve capacitance matching in SC filters. 59-64
Biomedical devices
- Alfredo Arnaud, Martin Bremermann, Joel Gak, Matías R. Miguez:
On the design of ultra low noise amplifiers for ENG recording. 65-70 - César Augusto Prior, Cesar Ramos Rodrigues, João Baptista dos Santos Martins, André Luiz Aita, Filipe Costa Beber Vieira:
Design of an integrated low power high CMRR instrumentation amplifier for biomedical applications. 71-75 - Daniel N. Ruiz, Robson L. Moreno, Tales Cleber Pimenta:
Design of a class D amplifier for hearing aid devices. 76-80
Design automation tools
- Marcio Ferreira da Silva Oliveira, Eduardo Wenzel Brião, Francisco Assis Moreira do Nascimento, Flávio Rech Wagner:
Model driven engineering for MPSOC design space exploration. 81-86 - Guilherme Flach, Marcelo O. Johann, Renato Fernandes Hentschke, Ricardo Reis:
Cell placement on graphics processing units. 87-92 - Leomar S. da Rosa Jr., André Inácio Reis, Renato P. Ribas, Felipe de Souza Marques, Felipe Ribeiro Schneider:
A comparative study of CMOS gates with minimum transistor stacks. 93-98
Circuits for communications - part 1
- Leonel Tedesco, Fernando Moraes, Ney Calazans:
Buffer sizing for QoS flows in wormhole packet switching NoCs. 99-104 - Edgard de Faria Corrêa, Leonardo Alves de Paula e Silva, Flávio Rech Wagner, Luigi Carro:
Fitting the router characteristics in NoCs to meet QoS requirements. 105-110 - Everton Carara, Fernando Moraes, Ney Calazans:
Router architecture for high-performance NoCs. 111-116
Circuits for communications - part 2
- Walter J. Lancioni, Pablo A. Petrashin, Luis E. Toledo, Carlos Dualibe:
A 9.6 kb/s CMOS FSK modem for data transmission through power lines. 117-122 - Fernando P. H. de Miranda, João Navarro Jr., Wilhelmus A. M. Van Noije:
A 4.1 GHz prescaler using double data throughput E-TSPC structures. 123-127 - Chithrupa Ramesh, Ana Rusu, Mohammed Ismail, Mikael Skoglund:
TrACS: transceiver architecture and wireless channel simulator. 128-132
Circuits for communications - part 3
- Pietro Maris Ferreira, Antonio Petraglia, Fernando Antonio Pinto Barúqui:
A CMOS AM demodulator for instrumentation applications. 133-136 - Juan Pablo Martinez Brito, Sergio Bampi:
Design of a digital FM demodulator based on a 2nddegree order all-digital phase-locked loop. 137-141 - Jose Marcelo Lima Duarte, Francisco das Chagas Mota, Manoel J. M. Carvalho:
Digital PM demodulator for brazilian data collecting system. 142-146
Reconfigurable logic and FPGAs - part 1
- Sudhakar Maddi, M. B. Srinivas:
A unified and reconfigurable Montgomery Multiplier architecture without four-to-two CSA. 147-152 - Florian Dittmann, Achim Rettberg, Raphael Weber:
Optimization techniques for a reconfigurable, self-timed, and bit-serial architecture. 153-158 - Monica Magalhães Pereira, Bruno Cruz de Oliveira, Ivan Saraiva Silva:
RoSA: a reconfigurable stream-based architecture. 159-164
Reconfigurable logic and FPGAs - part 2
- Christoforos Kachris, Stamatis Vassiliadis:
A reconfigurable platform for multi-service edge routers. 165-170 - Jordana L. Seixas, Edson Barbosa, Stelita M. da Silva, Paulo Sérgio B. do Nascimento, Vinícius Kursancew, Remy Eskinazi Sant'Anna, Edna Barros, Manoel Eusébio de Lima:
Aquarius: a dynamically reconfigurable computing platform. 171-176 - Christophe Bobda, Thomas Haller, Felix Mühlbauer, Dennis Rech, Simon Jung:
Design of adaptive multiprocessor on chip systems. 177-183
Device modeling and simulation - part 1
- K. S. Sainarayanan, Chittarsu Raghunandan, M. B. Srinivas:
Bus encoding schemes for minimizing delay in VLSI interconnects. 184-189 - Egas Henes Neto, Fernanda Lima Kastensmidt, Gilson I. Wirth:
A built-in current sensor for high speed soft errors detection robust to process and temperature variations. 190-195 - Jens Petter Abrahamsen, Tor Sverre Lande:
Soft-well digital circuit design. 196-201 - Jose M. Marulanda, Ashok Kumar Srivastava, Ashwani K. Sharma:
Transfer characteristics and high frequency modeling of logic gates using carbon nanotube field effect transistors (CNT-FETs). 202-206
Device modeling and simulation - part 2
- J. V. R. Ravindra, Srinivas Bala Mandalika:
Modeling and analysis of crosstalk for distributed RLC interconnects using difference model approach. 207-211 - Humberto Campanella, Arantxa Uranga, Pascal Nouet, Pedro De Paco Sanchez, Núria Barniol, Jaume Esteve:
Instantaneous de-embedding of the on-wafer equivalent-circuit parameters of acoustic resonator (FBAR) for integrated circuit applications. 212-217 - Alexandre Nentchev, Siegfried Selberherr:
Three-dimensional on-chip inductance and resistance extraction. 218-223
Neural nets and intelligent systems
- Dimitrios N. Loizos, Paul-Peter Sotiriadis, Gert Cauwenberghs:
High-speed, model-free adaptive control using parallel synchronous detection. 224-229 - Marcio Barbosa Lucks, Nobuo Oki:
Radial basis function network applied to the linearization of a voltage controlled oscillator. 230-235 - Hugo de Lemos Haas, José Gabriel Rodríguez Carneiro Gomes, Antonio Petraglia:
Viability of analog inner product operations in CMOS imagers. 236-240 - Julio Saldaña Pumarica, Emílio Del Moral Hernandez, Carlos Silva Cárdenas:
CMOS encoder for scale-independent pattern recognition. 241-244
Processing and layout techniques - part 1
- Agnes Sarolta Nagy, Alicia Polanco, Manuel Alvarez:
Contributions to improve design accuracy of bipolar ics via physical effects. 245-250 - Juan Núñez, José M. Quintana, Maria J. Avedillo:
A quasi-differential quantizer based on SMOBILE. 251-256
Processing and layout techniques - part 2
- Leo Huf Campos Braga, Suzana Domingues, Milton F. Rocha, Leonardo Bruno de Sá, Fernando de Souza Campos, Filipe V. Santos, Antonio Carneiro de Mesquita Filho, Mário Vaz Silva, Jacobus W. Swart:
Layout techniques for radiation hardening of standard CMOS active pixel sensors. 257-262 - John M. Espinosa-Duran, Jaime Velasco-Medina, Gloria Huertas, José Luis Huertas:
Total ionizing dose effects in switched-capacitor filters using oscillation-based test. 263-266
RF circuits
- C. N. M. Marins, Luiz C. Kretly:
Minimizing the mismatch errors at the VCO and cascode buffer connections in front end of BiCMOS RFICs operating on S band. 267-270 - Fernando da Rocha Paixão Cortes, Sergio Bampi:
A fully integrated CMOS RF front-end for a multi-band analog mixed-signal interface. 271-275 - César A. M. Marcon, José Carlos S. Palma, Fabiano Hessel, Eduardo A. Bezerra, Guilherme Rohde, Carlos Eduardo Reif, Luciano Azevedo, Carolina Metzler:
A 915 MHz UHF low power RFID tag. 276-281
SoCs and embedded systems - part 1
- Daniel Barcelos, Eduardo Wenzel Brião, Flávio Rech Wagner:
A hybrid memory organization to enhance task migration and dynamic task allocation in NoC-based MPSoCs. 282-287 - Gustavo Girão, Bruno Cruz de Oliveira, Rodrigo Soares, Ivan Saraiva Silva:
Cache coherency communication cost in a NoC-based MPSoC platform. 288-293 - Xiangrong Zhou, Peter Petrov:
The interval page table: virtual memory support in real-time and memory-constrained embedded systems. 294-299 - Costas Argyrides, Carlos Arthur Lang Lisbôa, Luigi Carro, Dhiraj K. Pradhan:
A soft error robust and power aware memory design. 300-305
SoCs and embedded systems - part 2
- Nathaniel Ross Pinckney, David Money Harris:
Parallelized radix-4 scalable montgomery multipliers. 306-311 - Eduardo Tavares, Paulo Romero Martins Maciel, Bruno Silva, Meuse N. Oliveira Jr.:
A time petri net-based approach for hard real-time systems scheduling considering dynamic voltage scaling, overheads, precedence and exclusion relations. 312-317 - Júlio C. B. de Mattos, Luigi Carro:
Object and method exploration for embedded systems applications. 318-323 - Emilena Specht, Ricardo Miotto Redin, Luigi Carro, Luís da Cunha Lamb, Érika F. Cota, Flávio Rech Wagner:
Analysis of the use of declarative languages for enhanced embedded system software development. 324-329
SoCs and embedded systems - part 3
- Leandro Soares Indrusiak, Manfred Glesner:
Specification of alternative execution semantics of UML sequence diagrams within actor-oriented models. 330-335 - Germano Guimarães, João Paulo Silva do Monte Lima, João Marcelo X. N. Teixeira, Guilherme D. Silva, Veronica Teichrieb, Judith Kelner:
FPGA infrastructure for the development of augmented reality applications. 336-341
Circuit test and verification
- Letícia Maria Veiras Bolzani, Paolo Bernardi, Matteo Sonza Reorda:
An optimized hybrid approach to provide fault detection and correction in SoCs. 342-347 - Letícia Maria Veiras Bolzani, Edgar E. Sánchez, Matteo Sonza Reorda:
A software-based methodology for the generation of peripheral test sets based on high-level descriptions. 348-353 - Lorenzo Petroli, Carlos Arthur Lang Lisbôa, Fernanda Lima Kastensmidt, Luigi Carro:
Using majority logic to cope with long duration transient faults. 354-359 - George Sobral Silveira, Karina R. G. da Silva, Elmar U. K. Melcher:
Functional verification of an MPEG-4 decoder design using a random constrained movie generator. 360-364
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