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ORCIDIET Computers & Digital Techniques, Volume 11
Volume 11, Number 1, January 2017
- Bahar Asgari, Mahdi Fazeli
, Ahmad Patooghy, Seyed Vahid Azhari:
Micro-architectural approach to the efficient employment of STTRAM cells in a microprocessor register file. 1-7 - Hao Xiao, Busheng Zheng, Tsuyoshi Isshiki, Hiroaki Kunieda:
Hybrid shared-memory and message-passing multiprocessor system-on-chip for UWB MAC layer. 8-15 - Pawan Singh, Nirayo Hailu Gebreegziabher:
Energy-aware online non-clairvoyant multiprocessor scheduling: multiprocessor priority round robin. 16-23 - Gaizhen Yan, Ning Wu, Fen Ge, Hao Xiao, Fang Zhou:
Collaborative fuzzy-based partially-throttling dynamic thermal management scheme for three-dimensional networks-on-chip. 24-32 - Md. Selim Hossain, Yinan Kong, Ehsan Saeedi, Cheeckottu Vayalil Niras:
High-performance elliptic curve cryptography processor over NIST prime fields. 33-42 - Ranjan Kumar Barik, Manoranjan Pradhan:
Efficient ASIC and FPGA implementation of cube architecture. 43-49
Volume 11, Number 2, March 2017
- Cong Ma, William Tuohy, David J. Lilja:
Impact of spintronic memory on multicore cache hierarchy design. 51-59 - Yu-Cheng Liu, Cheng-Yu Han, Shih-Ya Lin, James Chien-Mo Li:
PSN-aware circuit test timing prediction using machine learning. 60-67 - Anirban Sengupta, Saumya Bhadauria, Saraju P. Mohanty:
Low-cost security aware HLS methodology. 68-79
Volume 11, Number 3, May 2017
- Irith Pomeranz:
Reconstruction of a functional test sequence for increased fault coverage. 91-97 - Irith Pomeranz:
Metric for the ability of functional capture cycles to ensure functional operation conditions. 100-106 - Chintan A. Parmar, Bhaskar Ramanadham, Anand D. Darji:
FPGA implementation of hardware efficient adaptive filter robust to impulsive noise. 107-116 - Qiang Liu, HanJing Qian:
Fast and accurate circuit delay model for FPGA architectural exploration. 117-123
Volume 11, Number 4, July 2017
- Haythem Bahri, Fatma Sayadi, Randa Khemiri, Marwa Chouchene, Mohamed Atri:
Image feature extraction algorithm based on CUDA architecture: case study GFD and GCFD. 125-132 - Giovani Gracioli, Antônio Augusto Fröhlich:
Two-phase colour-aware multicore real-time scheduler. 133-139 - Usman Ali Gulzari, Sheraz Anjum, Shahrukh Agha, Sarzamin Khan, Frank Sill Torres:
Efficient and scalable cross-by-pass-mesh topology for networks-on-chip. 140-148 - Hao Zhang, Dongdong Chen, Seok-Bum Ko:
Area- and power-efficient iterative single/double-precision merged floating-point multiplier on FPGA. 149-158 - Aiman H. El-Maleh:
Finite state machine-based fault tolerance technique with enhanced area and power of synthesised sequential circuits. 159-164
Volume 11, Number 5, September 2017
- Shahzad Asif, Md. Selim Hossain, Yinan Kong:
High-throughput multi-key elliptic curve cryptosystem based on residue number system. 165-172 - Rym Chéour, Mohamed Wassim Jmal, Olfa Kanoun, Mohamed Abid:
Evaluation of simulator tools and power-aware scheduling model for wireless sensor networks. 173-182 - M. Mohamed Asan Basiri, S. K. Noor Mohammad:
Quadruple throughput fixed point quarter precision multiply accumulate circuit design. 183-189 - Liang-Ying Lu, Lih-Yih Chiou:
Temperature gradient-aware thermal simulator for three-dimensional integrated circuits. 190-196 - Shaista Jabeen, Sudarshan K. Srinivasan, Sana Shuja:
Formal verification methodology for real-time Field Programmable Gate Array. 197-203
Volume 11, Number 6, November 2017
- Mustapha Bourahla:
LTL transformation modulo positive transitions. 205-213 - Imtiaz Ahmad, Mahmoud Imdoukh, Mohammad AlFailakawi:
Extending multi-level STT-MRAM cell lifetime by minimising two-step and hard state transitions in hot bits. 214-220 - Ionel Zagan, Vasile Gheorghita Gaitan:
Implementation of nMPRA CPU architecture based on preemptive hardware scheduler engine and different scheduling algorithms. 221-230 - Temesgen Seyoum Alemayehu, Jai-Hoon Kim:
Dependability analysis of cyber physical systems. 231-236
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