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ORCIDSaumya Bhadauria
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2020 – today
- 2024
[j11]Himanshu Gauttam
, K. K. Pattanaik, Saumya Bhadauria, Garima Nain:
SCL: A sustainable deep learning solution for edge computing ecosystem in smart manufacturing. J. Ind. Inf. Integr. 42: 100703 (2024)- 2023
- [j10]Himanshu Gauttam, Kiran Kumar Pattanaik, Saumya Bhadauria, Garima Nain, Putta Bhanu Prakash:
An efficient DNN splitting scheme for edge-AI enabled smart manufacturing. J. Ind. Inf. Integr. 34: 100481 (2023) - 2022
- [j9]Pulkit Rathi, Saumya Bhadauria, Sugandha Rathi:
Watermarking of Deep Recurrent Neural Network Using Adversarial Examples to Protect Intellectual Property. Appl. Artif. Intell. 36(1) (2022) - [j8]Himanshu Gauttam, K. K. Pattanaik, Saumya Bhadauria, Divya Saxena, Sapna:
A cost aware topology formation scheme for latency sensitive applications in edge infrastructure-as-a-service paradigm. J. Netw. Comput. Appl. 199: 103303 (2022) - [c15]Ojaswa Sharma, Mudit Verma, Saumya Bhadauria, Praveen Jayachandran:
A Guided Approach Towards Complex Chaos Selection, Prioritisation and Injection. CLOUD 2022: 91-93 - 2021
- [c14]Saumya Bhadauria, Pranjal Kumar, Tamanna Mohanty:
Intellectual Property Protection using Blockchain and Digital Watermarking. ANTS 2021: 1-6 - [c13]Saumya Bhadauria, Tamanna Mohanty:
Hybrid Intrusion Detection System using an Unsupervised method for Anomaly-based Detection. ANTS 2021: 1-6 - 2020
- [c12]Kratika Sharma, Saumya Bhadauria:
Detection and Prevention of Black Hole Attack in SUPERMAN. IEEE ANTS 2020: 1-6
2010 – 2019
- 2019
- [c11]Sanket Rai, Aditya Gupta, Abhinav Anand, Aditya Trivedi, Saumya Bhadauria:
Demand prediction for e-commerce advertisements: A comparative study using state-of-the-art machine learning methods. ICCCNT 2019: 1-6 - [c10]Justin Joseph, Saumya Bhadauria:
Cookie Based Protocol to Defend Malicious Browser Extensions. ICCST 2019: 1-6 - 2018
- [c9]Saumya Bhadauria, Ansuya Bohra:
Secure Hierarchical VANETs. ANTS 2018: 1-5 - 2017
- [j7]Anirban Sengupta, Saumya Bhadauria, Saraju P. Mohanty:
Low-cost security aware HLS methodology. IET Comput. Digit. Tech. 11(2): 68-79 (2017) - [j6]Anirban Sengupta, Dipanjan Roy, Saumya Bhadauria:
Low cost optimized Trojan secured schedule at behavioral level for single & Nested loop control data flow graphs (Invited Paper). Integr. 58: 378-389 (2017) - [j5]Anirban Sengupta, Saumya Bhadauria, Saraju P. Mohanty:
TL-HLS: Methodology for Low Cost Hardware Trojan Security Aware Scheduling With Optimal Loop Unrolling Factor During High Level Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(4): 655-668 (2017) - 2016
- [j4]Anirban Sengupta, Saumya Bhadauria:
Exploring Low Cost Optimal Watermark for Reusable IP Cores During High Level Synthesis. IEEE Access 4: 2198-2215 (2016) - [c8]Anirban Sengupta, Saumya Bhadauria, Saraju P. Mohanty:
Embedding low cost optimal watermark during high level synthesis for reusable IP core protection. ISCAS 2016: 974-977 - 2015
- [j3]Anirban Sengupta, Saumya Bhadauria:
Automated design space exploration of multi-cycle transient fault detectable datapath based on multi-objective user constraints for application specific computing. Adv. Eng. Softw. 82: 14-24 (2015) - [j2]Saumya Bhadauria, Anirban Sengupta:
Adaptive bacterial foraging driven datapath optimization: Exploring power-performance tradeoff in high level synthesis. Appl. Math. Comput. 269: 265-278 (2015) - [j1]Anirban Sengupta, Saumya Bhadauria:
Bacterial foraging driven exploration of multi cycle fault tolerant datapath based on power-performance tradeoff in high level synthesis. Expert Syst. Appl. 42(10): 4719-4732 (2015) - [c7]Anirban Sengupta, Saumya Bhadauria:
Untrusted Third Party Digital IP Cores: Power-Delay Trade-off Driven Exploration of Hardware Trojan Secured Datapath during High Level Synthesis. ACM Great Lakes Symposium on VLSI 2015: 167-172 - [c6]Anirban Sengupta, Saumya Bhadauria:
Secure Information Processing during System-Level: Exploration of an Optimized Trojan Secured Datapath for CDFGs during HLS Based on User Constraints. iNIS 2015: 1-6 - [c5]Anirban Sengupta, Saumya Bhadauria:
User power-delay budget driven PSO based design space exploration of optimal k-cycle transient fault secured datapath during high level synthesis. ISQED 2015: 289-292 - [c4]Anirban Sengupta, Saumya Bhadauria:
Automated design space exploration of transient fault detectable datapath based on user specified power and delay constraints. VLSI-DAT 2015: 1-4 - 2014
- [c3]Anirban Sengupta, Saumya Bhadauria:
Automated exploration of datapath in high level synthesis using temperature dependent bacterial foraging optimization algorithm. CCECE 2014: 1-5 - [c2]Anirban Sengupta, Saumya Bhadauria:
Error Masking of Transient Faults: Exploration of a Fault Tolerant Datapath Based on User Specified Power and Delay Budget. ICIT 2014: 345-350 - [c1]Anirban Sengupta, Saumya Bhadauria:
Exploration of Multi-objective Tradeoff during High Level Synthesis Using Bacterial Chemotaxis and Dispersal. KES 2014: 63-72
Coauthor Index
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