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ORCIDInternational Journal of Reconfigurable Computing, Volume 2009
Volume 2009, 2009
- Shuli Gao, Dhamin Al-Khalili, Noureddine Chabini:
Efficient Scheme for Implementing Large Size Signed Multipliers Using Multigranular Embedded DSP Blocks in FPGAs. 145130:1-145130:11 - Imran Rafiq Quadri, Samy Meftali, Jean-Luc Dekeyser:
High level modeling of Dynamic Reconfigurable FPGAs. 408605:1-408605:15 - Jim Harkin, Fearghal Morgan, Liam McDaid, Steve Hall, Brian McGinley, Seamus Cawley:
A Reconfigurable and Biologically Inspired Paradigm for Computation Using Network-On-Chip and Spiking Neural Networks. Int. J. Reconfigurable Comput. 2009: 908740:1-908740:13 (2009) - Christopher Pohl, Carlos Paiz, Mario Porrmann
:
vMAGIC - Automatic Code Generation for VHDL. 205149:1-205149:9 - Damien Picard, Loïc Lagadec:
Multilevel Simulation of Heterogeneous Reconfigurable Platforms. 162416:1-162416:12 - Thilo Pionteck, Roman Koch, Carsten Albrecht, Erik Maehle:
A Design Technique for Adapting Number and Boundaries of Reconfigurable Modules at Runtime. 942930:1-942930:10 - Gabriel Marchesan Almeida, Gilles Sassatelli, Pascal Benoit, Nicolas Saint-Jean, Sameer Varyani, Lionel Torres, Michel Robert:
An Adaptive Message Passing MPSoC Framework. 242981:1-242981:20 - Diana Göhringer, Thomas Perschke, Michael Hübner, Jürgen Becker:
A Taxonomy of Reconfigurable Single-/Multiprocessor Systems-on-Chip. 395018:1-395018:11 - Fernando Martin del Campo, René Cumplido, Roberto Perez-Andrade, Aldo G. Orozco-Lugo:
A System on a Programmable Chip Architecture for Data-Dependent Superimposed Training Channel Estimation. 912301:1-912301:10 - Peter Zipf, Gilles Sassatelli, Nurten Utlu, Nicolas Saint-Jean, Pascal Benoit, Manfred Glesner:
A Decentralised Task Mapping Approach for Homogeneous Multiprocessor Network-On-Chips. 453970:1-453970:14 - Arvind Sudarsanam, Aravind Dasu, Karthik Vaithianathan:
Analysis and Design of a Context Adaptable SAD/MSE Architecture. 789592:1-789592:21 - Kurt Franz Ackermann, Burghard Hoffmann, Leandro Soares Indrusiak, Manfred Glesner:
Providing Memory Management Abstraction for Self-Reconfigurable Video Processing Platforms. 851613:1-851613:15 - Manuel Saldaña, Emanuel Ramalho, Paul Chow:
A Message-Passing Hardware/Software Cosimulation Environment for Reconfigurable Computing Systems. 376232:1-376232:9 - Yi-Hua Edward Yang, Viktor K. Prasanna:
Software Toolchain for Large-Scale RE-NFA Construction on FPGA. 301512:1-301512:10 - Knut Wold, Chik How Tan:
Analysis and Enhancement of Random Number Generator in FPGA Based on Oscillator Rings. 501672:1-501672:8 - Huong Ho, Valek Szwarc, Tad A. Kwasniewski:
A Reconfigurable Systolic Array Architecture for Multicarrier Wireless and Multirate Applications. 529512:1-529512:14 - Bin Zhou, Yingning Peng, David Hwang:
Pipeline FFT Architectures Optimized for FPGAs. 219140:1-219140:9 - Marcel D. van de Burgwal, Pascal T. Wolkotte, Gerard J. M. Smit:
Non-Power-of-Two FFTs: Exploring the Flexibility of the Montium TP. 678045:1-678045:12 - Zied Marrakchi, Hayder Mrabet, Umer Farooq, Habib Mehrez:
FPGA Interconnect Topologies Exploration. 259837:1-259837:13 - Christophe Bobda, Kevin Cheng, Felix Mühlbauer, Klaus Drechsler, Jan Schulte, Dominik Murr, Camel Tanougast:
Enabling Self-Organization in Embedded Systems with Reconfigurable Hardware. 161458:1-161458:9 - Ashwin A. Mendon, Andrew G. Schmidt, Ron Sass:
A Hardware Filesystem Implementation with Multidisk Support. 572860:1-572860:13 - Christian Schuck, Bastian Haetzer, Jürgen Becker:
An Interface for a Decentralized 2D Reconfiguration on Xilinx Virtex-FPGAs for Organic Computing. 273791:1-273791:11 - Harold Ishebabi, Philipp Mahr, Christophe Bobda, Martin Gebser, Torsten Schaub:
Answer Set versus Integer Linear Programming for Automatic Synthesis of Multiprocessor Systems from Real-Time Parallel Programs. 863630:1-863630:11 - Stéphane Chevobbe, Stéphane Guyetant:
Reducing Reconfiguration Overheads in Heterogeneous Multicore RSoCs with Predictive Configuration Management. 390167:1-390167:7 - Xinyu Li, Omar Hammami:
An Automatic Design Flow for Data Parallel and Pipelined Signal Processing Applications on Embedded Multiprocessor with NoC: Application to Cryptography. 631490:1-631490:14 - Gabriel Caffarena, Juan A. López, Gerardo Leyva, Carlos Carreras, Octavio Nieto-Taladriz:
Architectural Synthesis of Fixed-Point DSP Datapaths Using FPGAs. 703267:1-703267:14 - Francesco Redaelli, Marco D. Santambrogio, Seda Ogrenci Memik:
An ILP Formulation for the Task Graph Scheduling Problem Tailored to Bi-Dimensional Reconfigurable Architectures. 541067:1-541067:12 - Erwan Fabiani:
Experiencing a Problem-Based Learning Approach for Teaching Reconfigurable Architecture Design. 923415:1-923415:11 - Jose Hugo Barron-Zambrano, Fernando Martin del Campo-Ramirez, Miguel O. Arias-Estrada:
Parallel Processor for 3D Recovery from Optical Flow. 973475:1-973475:11 - Scott Lloyd, Quinn Snell:
Hardware Accelerated Sequence Alignment with Traceback. 762362:1-762362:10 - Michael Hübner, Juan Manuel Moreno, Gilles Sassatelli, Peter Zipf:
Selected Papers from ReCoSoC 2008. 894059:1-894059:2 - Cristinel Ababei:
Speeding Up FPGA Placement via Partitioning and Multithreading. 514754:1-514754:9 - Bernard Girau, César Torres-Huitzil, Nikolaos Vlassopoulos, Jose Hugo Barron-Zambrano:
Reaction Diffusion and Chemotaxis for Decentralized Gathering on FPGAs. 639249:1-639249:15 - Benoît Miramond, Emmanuel Huck, François Verdier, Mohamed El Amine Benkhelifa, Bertrand Granado, Thomas LeFebvre, Mehdi Aïchouch, Jean-Christophe Prévotet, Yaset Oliva, Daniel Chillet, Sébastien Pillement:
OveRSoC: A Framework for the Exploration of RTOS for RSoC Platforms. 450607:1-450607:22 - Lionel Torres, César Torres:
Selected Papers from ReConFig 2008. 869329:1-869329:2
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