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Integration, Volume 31

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Volume 31, Number 1, November 2001

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Jiang Hu, Sachin S. Sapatnekar:
A survey on multi-net global routing for integrated circuits. 1-49
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Rolf Drechsler, Wolfgang Günther:
History-based dynamic BDD minimization. 51-63
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Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu:
Floorplanning with abutment constraints based on corner block list. 65-77
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Luca Fanucci, Sergio Saponara, Lorenzo Bertini:
A parametric VLSI architecture for video motion estimation. 79-100

Volume 31, Number 2, May 2002

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José M. Mendías, Román Hermida, Olga Peñalba:
A study about the efficiency of formal high-level synthesis applied to verification. 101-131
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Yumin Zhang, Xiaobo Sharon Hu, Danny Z. Chen:
Cell selection from technology libraries for minimizing power. 133-158
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Suresh Raman, Sachin S. Sapatnekar, Charles J. Alpert:
Probability-driven routing in a datapath environment. 159-182
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  - journals/integration/TsiatouhasMHNA02
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Y. Tsiatouhas, Yiannis Moisiadis, Th. Haniotakis, Dimitris Nikolos, Angela Arapoyanni:
A new technique for IDDQ testing in nanometer technologies. 183-194

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