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2010 – 2019
- 2011
[j77]Kan Wang
, Sheqin Dong, Yuchun Ma, Yu Wang, Xianlong Hong, Jason Cong:
Leakage-Aware TSV-Planning with Power-Temperature-Delay Dependence in 3D ICs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 94-A(12): 2490-2498 (2011)- [c181]Kan Wang, Yuchun Ma, Sheqin Dong, Yu Wang, Xianlong Hong, Jason Cong:
Rethinking thermal via planning with timing-power-temperature dependence for 3D ICs. ASP-DAC 2011: 261-266 - 2010
- [j76]Shan Zeng, Wenjian Yu, Xianlong Hong, Chung-Kuan Cheng:
Efficient Power Network Analysis with Modeling of Inductive Effects. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(6): 1196-1203 (2010) - [j75]Yuchun Ma, Qiang Zhou, Pingqiang Zhou, Xianlong Hong:
Thermal Impacts of Leakage Power in 2D/3D floorplanning. J. Circuits Syst. Comput. 19(7): 1483-1495 (2010) - [j74]Shenghua Liu, Guoqiang Chen, Tom Tong Jing, Lei He, Robi Dutta, Xianlong Hong:
Effective congestion reduction for IC package substrate routing. ACM Trans. Design Autom. Electr. Syst. 15(3): 27:1-27:21 (2010) - [j73]Yin Shen, Qiang Zhou, Yici Cai, Xianlong Hong:
ECP- and CMP-Aware Detailed Routing Algorithm for DFM. IEEE Trans. Very Large Scale Integr. Syst. 18(1): 153-157 (2010) - [j72]Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu:
An Effective Gated Clock Tree Design Based on Activity and Register Aware Placement. IEEE Trans. Very Large Scale Integr. Syst. 18(12): 1639-1648 (2010) - [c180]Shenghua Liu, Yuchun Ma, Xianlong Hong, Yu Wang:
Simultaneous slack budgeting and retiming for synchronous circuits optimization. ASP-DAC 2010: 49-54 - [c179]Li Li, Yuchun Ma, Ning Xu, Yu Wang, Xianlong Hong:
PS-FPG: pattern selection based co-design of floorplan and power/ground network with wiring resource optimization. ASP-DAC 2010: 769-774
2000 – 2009
- 2009
- [j71]Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu, Bing Lu:
A single layer zero skew clock routing in X architecture. Sci. China Ser. F Inf. Sci. 52(8): 1466-1475 (2009) - [j70]Shan Zeng, Wenjian Yu, Jin Shi, Xianlong Hong, Chung-Kuan Cheng:
Efficient Partial Reluctance Extraction for Large-Scale Regular Power Grid Structures. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(6): 1476-1484 (2009) - [j69]Yuchun Ma, Xin Li, Yu Wang, Xianlong Hong:
Thermal-Aware Incremental Floorplanning for 3D ICs Based on MILP Formulation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(12): 2979-2989 (2009) - [j68]Haixia Yan, Qiang Zhou, Xianlong Hong:
Thermal aware placement in 3D ICs using quadratic uniformity modeling approach. Integr. 42(2): 175-180 (2009) - [j67]Qiang Zhou, Xin Zhao, Yici Cai, Xianlong Hong:
An MTCMOS technology for low-power physical design. Integr. 42(3): 340-345 (2009) - [j66]Shenghua Liu, Guoqiang Chen, Tom Tong Jing, Lei He, Tianpei Zhang, Robi Dutta, Xianlong Hong:
Substrate Topological Routing for High-Density Packages. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(2): 207-216 (2009) - [c178]Ruijing Shen, Ning Mi, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong:
Statistical modeling and analysis of chip-level leakage power by spectral stochastic method. ASP-DAC 2009: 161-166 - [c177]Xin Li, Yuchun Ma, Xianlong Hong:
A novel thermal optimization flow using incremental floorplanning for 3D ICs. ASP-DAC 2009: 347-352 - [c176]Hui Dai, Qiang Zhou, Yici Cai, Jinian Bian, Xianlong Hong:
Fast placement for large-scale hierarchical FPGAs. CAD/Graphics 2009: 190-194 - [c175]Xiaoyi Wang, Yici Cai, Sheldon X.-D. Tan, Xianlong Hong, Jacob Relles:
An efficient decoupling capacitance optimization using piecewise polynomial models. DATE 2009: 1190-1195 - [c174]Fubing Mao, Yuchun Ma, Ning Xu, Xianlong Hong, Yu Wang:
Multi-objective Floorplanning Based on Fuzzy Logic. FSKD (4) 2009: 331-335 - [c173]Sheqin Dong, Hongjie Bai, Xianlong Hong, Satoshi Goto:
Buffer Planning for 3D ICs. ISCAS 2009: 1735-1738 - [c172]Shenghua Liu, Guoqiang Chen, Tom Tong Jing, Lei He, Robi Dutta, Xianlong Hong:
Diffusion-driven congestion reduction for substrate topological routing. ISPD 2009: 175-180 - [c171]Yuchun Ma, Xiang Qiu, Xiangqing He, Xianlong Hong:
Incremental power optimization for multiple supply voltage design. ISQED 2009: 280-286 - [c170]Dawei Liu, Qiang Zhou, Jinian Bian, Yici Cai, Xianlong Hong:
Cell shifting aware of wirelength and overlap. ISQED 2009: 506-510 - [c169]Xu He, Sheqin Dong, Yuchun Ma, Xianlong Hong:
Simultaneous buffer and interlayer via planning for 3D floorplanning. ISQED 2009: 740-745 - [c168]Shan Zeng, Wenjian Yu, Wanping Zhang, Jian Wang, Xianlong Hong, Chung-Kuan Cheng:
Efficient power network analysis with complete inductive modeling. ISQED 2009: 770-775 - [c167]Li Li, Yuchun Ma, Ning Xu, Yu Wang, Xianlong Hong:
Modern Floorplanning with Boundary Clustering Constraint. ISVLSI 2009: 79-84 - [c166]Xu He, Sheqin Dong, Xianlong Hong, Satoshi Goto:
Integrated interlayer via planning and pin assignment for 3D ICs. SLIP 2009: 99-104 - 2008
- [j65]Yici Cai, Qiang Zhou, Xianlong Hong, Rui Shi, Yang Wang:
Application of optical proximity correction technology. Sci. China Ser. F Inf. Sci. 51(2): 213-224 (2008) - [j64]Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu:
Low Power Gated Clock Tree Driven Placement. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(2): 595-603 (2008) - [j63]Liangpeng Guo, Yici Cai, Qiang Zhou, Xianlong Hong:
Logic and Layout Aware Level Converter Optimization for Multiple Supply Voltage. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(8): 2084-2090 (2008) - [j62]Xiaoyi Wang, Jin Shi, Yici Cai, Xianlong Hong:
Early Stage Power Supply Planning: A Heuristic Method for Codesign of Power/Ground Network and Floorplan. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(12): 3443-3450 (2008) - [j61]Yanming Jia, Yici Cai, Xianlong Hong:
Dummy Fill Aware Buffer Insertion after Layer Assignment Based on an Effective Estimation Model. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(12): 3783-3792 (2008) - [j60]Hailong Yao, Subarna Sinha, Jingyu Xu, Charles C. Chiang, Yici Cai, Xianlong Hong:
Efficient range pattern matching algorithm for process-hotspot detection. IET Circuits Devices Syst. 2(1): 2-15 (2008) - [j59]Yici Cai, Jin Shi, Zhu Pan, Xianlong Hong, Sheldon X.-D. Tan:
Large scale P/G grid transient simulation using hierarchical relaxed approach. Integr. 41(1): 153-160 (2008) - [j58]Tom Tong Jing, Yu Hu, Zhe Feng, Xianlong Hong, Xiaodong Hu, Guiying Yan:
A full-scale solution to the rectilinear obstacle-avoiding Steiner problem. Integr. 41(3): 413-425 (2008) - [j57]Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu, Bing Lu:
Zero skew clock routing in X-architecture based on an improved greedy matching algorithm. Integr. 41(3): 426-438 (2008) - [j56]Zhen Cao, Tong Jing, Jinjun Xiong, Yu Hu, Zhe Feng, Lei He, Xianlong Hong:
Fashion: A Fast and Accurate Solution to Global Routing Problem. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(4): 726-737 (2008) - [j55]Ning Mi, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong:
Fast Variational Analysis of On-Chip Power Grids by Stochastic Extended Krylov Subspace Method. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(11): 1996-2006 (2008) - [j54]Yici Cai, Le Kang, Jin Shi, Xianlong Hong, Sheldon X.-D. Tan:
Random Walk Guided Decap Embedding for Power/Ground Network Optimization. IEEE Trans. Circuits Syst. II Express Briefs 55-II(1): 36-40 (2008) - [j53]Ning Mi, Jeffrey Fan, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong:
Statistical Analysis of On-Chip Power Delivery Networks Considering Lognormal Leakage Current Variations With Spatial Correlation. IEEE Trans. Circuits Syst. I Regul. Pap. 55-I(7): 2064-2075 (2008) - [c165]Changdao Dong, Qiang Zhou, Yici Cai, Xianlong Hong:
Wire density driven top-down global placement for CMP variation control. APCCAS 2008: 1676-1679 - [c164]Xin Li, Yuchun Ma, Xianlong Hong, Sheqin Dong, Jason Cong:
LP based white space redistribution for thermal via planning and performance optimization in 3D ICs. ASP-DAC 2008: 209-212 - [c163]Yanfeng Wang, Qiang Zhou, Yici Cai, Jiang Hu, Xianlong Hong, Jinian Bian:
Low power clock buffer planning methodology in F-D placement for large scale circuit design. ASP-DAC 2008: 370-375 - [c162]Xiaoyi Wang, Jin Shi, Yici Cai, Xianlong Hong:
Heuristic power/ground network and floorplan co-design method. ASP-DAC 2008: 617-622 - [c161]Shuai Li, Jin Shi, Yici Cai, Xianlong Hong:
Vertical via design techniques for multi-layered P/G networks. ASP-DAC 2008: 623-628 - [c160]Jiayi Liu, Sheqin Dong, Xianlong Hong, Yibo Wang, Ou He, Satoshi Goto:
Symmetry constraint based on mismatch analysis for analog layout in SOI technology. ASP-DAC 2008: 772-775 - [c159]Shenghua Liu, Guoqiang Chen, Tom Tong Jing, Lei He, Tianpei Zhang, Robi Dutta, Xianlong Hong:
Topological routing to maximize routability for package substrate. DAC 2008: 566-569 - [c158]Xing Wei, Juanjuan Chen, Qiang Zhou, Yici Cai, Jinian Bian, Xianlong Hong:
MacroMap: A technology mapping algorithm for heterogeneous FPGAs with effective area estimation. FPL 2008: 559-562 - [c157]Liangpeng Guo, Yici Cai, Qiang Zhou, Le Kang, Xianlong Hong:
A novel performance driven power gating based on distributed sleep transistor network. ACM Great Lakes Symposium on VLSI 2008: 255-260 - [c156]Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu:
Gate planning during placement for gated clock network. ICCD 2008: 128-133 - [c155]Weixiang Shen, Yici Cai, Xianlong Hong:
Leakage power optimization for clock network using dual-Vth technology. ISCAS 2008: 2769-2772 - [c154]Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu:
Activity and register placement aware gated clock network design. ISPD 2008: 182-189 - [c153]Haixia Yan, Qiang Zhou, Xianlong Hong:
Efficient Thermal Aware Placement Approach Integrated with 3D DCT Placement Algorithm. ISQED 2008: 289-292 - [c152]Yin Shen, Yici Cai, Qiang Zhou, Xianlong Hong:
DFM Based Detailed Routing Algorithm for ECP and CMP. ISQED 2008: 357-360 - [c151]Xiang Qiu, Yuchun Ma, Xiangqing He, Xianlong Hong:
IPOSA: A Novel Slack Distribution Algorithm for Interconnect Power Optimization. ISQED 2008: 873-876 - [c150]Yibo Wang, Yici Cai, Xianlong Hong:
A Low-Power Buffered Tree Construction Algorithm Aware of Supply Voltage Variation. ISVLSI 2008: 221-226 - [c149]Yanming Jia, Yici Cai, Xianlong Hong:
Full-chip routing system for reducing Cu CMP & ECP variation. SBCCI 2008: 10-15 - 2007
- [j52]Yici Cai, Bin Liu, Qiang Zhou, Xianlong Hong:
Voltage Island Generation in Cell Based Dual-Vdd Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(1): 267-273 (2007) - [j51]Yibo Wang, Yici Cai, Xianlong Hong, Yi Zou:
Stochastic Interconnect Tree Construction Algorithm with Accurate Delay and Power Consideration. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(5): 1028-1037 (2007) - [j50]Yongqiang Lu, Xianlong Hong, Qiang Zhou, Yici Cai, Jun Gu:
An efficient quadratic placement based on search space traversing technology. Integr. 40(3): 253-260 (2007) - [j49]Yaoguang Wei, Sheqin Dong, Xianlong Hong:
APWL-Y: An accurate and efficient wirelength estimation technique for hexagon/triangle placement. Integr. 40(4): 406-419 (2007) - [j48]Jeffrey Fan, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong:
Partitioning-based decoupling capacitor budgeting via sequence of linear programming. Integr. 40(4): 516-524 (2007) - [j47]Qiang Zhou, Yici Cai, Duo Li, Xianlong Hong:
A Yield-Driven Gridless Router. J. Comput. Sci. Technol. 22(5): 653-660 (2007) - [j46]Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Shan Zeng, Jinian Bian, Wenjian Yu, Hannah Honghua Yang, Vijay Pitchumani, Chung-Kuan Cheng:
Efficient Thermal via Planning Approach and Its Application in 3-D Floorplanning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(4): 645-658 (2007) - [j45]Jin Shi, Yici Cai, Sheldon X.-D. Tan, Jeffrey Fan, Xianlong Hong:
Pattern-Based Iterative Method for Extreme Large Power/Ground Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(4): 680-692 (2007) - [j44]Tom Tong Jing, Zhe Feng, Yu Hu, Xianlong Hong, Xiaodong Hu, Guiying Yan:
lambda-OAT: lambda-Geometry Obstacle-Avoiding Tree Construction With O(nlog n) Complexity. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(11): 2073-2079 (2007) - [c148]Jiayi Liu, Sheqin Dong, Yuchun Ma, Di Long, Xianlong Hong:
Thermal-driven Symmetry Constraint for Analog Layout with CBL Representation. ASP-DAC 2007: 191-196 - [c147]Zhen Cao, Tong Jing, Jinjun Xiong, Yu Hu, Lei He, Xianlong Hong:
DpRouter: A Fast and Accurate Dynamic-Pattern-Based Global Routing Algorithm. ASP-DAC 2007: 256-261 - [c146]Yi Zou, Yici Cai, Qiang Zhou, Xianlong Hong, Sheldon X.-D. Tan, Le Kang:
Practical Implementation of Stochastic Parameterized Model Order Reduction via Hermite Polynomial Chaos. ASP-DAC 2007: 367-372 - [c145]Liangpeng Guo, Yici Cai, Qiang Zhou, Xianlong Hong:
Logic and Layout Aware Voltage Island Generation for Low Power Design. ASP-DAC 2007: 666-671 - [c144]Le Kang, Yici Cai, Yi Zou, Jin Shi, Xianlong Hong, Sheldon X.-D. Tan:
Fast Decoupling Capacitor Budgeting for Power/Ground Network Using Random Walk Approach. ASP-DAC 2007: 751-756 - [c143]Yuchun Ma, Zhuoyuan Li, Jason Cong, Xianlong Hong, Glenn Reinman, Sheqin Dong, Qiang Zhou:
Micro-architecture Pipelining Optimization with Throughput-Aware Floorplanning. ASP-DAC 2007: 920-925 - [c142]Le Kang, Yici Cai, Jin Shi, Xianlong Hong, Sheldon X.-D. Tan, Xiaoyi Wang:
Simultaneous Switching Noise Consideration for Power/Ground Network Optimization. CAD/Graphics 2007: 332-337 - [c141]Pingqiang Zhou, Yuchun Ma, Qiang Zhou, Xianlong Hong:
Thermal Effects with Leakage Power Considered in 2D/3D Floorplanning. CAD/Graphics 2007: 338-343 - [c140]Jeffrey Fan, Ning Mi, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong:
Statistical model order reduction for interconnect circuits considering spatial correlations. DATE 2007: 1508-1513 - [c139]Yanming Jia, Yici Cai, Xianlong Hong:
Dummy fill aware buffer insertion during routing. ACM Great Lakes Symposium on VLSI 2007: 31-36 - [c138]Xinjie Wei, Yici Cai, Xianlong Hong:
Physical aware clock skew rescheduling. ACM Great Lakes Symposium on VLSI 2007: 473-476 - [c137]Ou He, Sheqin Dong, Jinian Bian, Yuchun Ma, Xianlong Hong:
An effective buffer planning algorithm for IP based fixed-outline SOC placement. ACM Great Lakes Symposium on VLSI 2007: 564-569 - [c136]Yue Zhuo, Hao Li, Qiang Zhou, Yici Cai, Xianlong Hong:
New timing and routability driven placement algorithms for FPGA synthesis. ACM Great Lakes Symposium on VLSI 2007: 570-575 - [c135]Ning Mi, Sheldon X.-D. Tan, Pu Liu, Jian Cui, Yici Cai, Xianlong Hong:
Stochastic extended Krylov subspace method for variational analysis of on-chip power grid networks. ICCAD 2007: 48-53 - [c134]Pingqiang Zhou, Yuchun Ma, Zhuoyuan Li, Robert P. Dick, Li Shang, Hai Zhou, Xianlong Hong, Qiang Zhou:
3D-STAF: scalable temperature and leakage aware floorplanning for three-dimensional integrated circuits. ICCAD 2007: 590-597 - [c133]Xinjie Wei, Yici Cai, Xianlong Hong:
Effective Acceleration of Iterative Slack Distribution Process. ISCAS 2007: 1077-1080 - [c132]Yanfeng Wang, Qiang Zhou, Xianlong Hong, Yici Cai:
Clock-Tree Aware Placement Based on Dynamic Clock-Tree Building. ISCAS 2007: 2040-2043 - [c131]Lingyi Zhang, Sheqin Dong, Xianlong Hong, Yuchun Ma:
A Fast 3D-BSG Algorithm for 3D Packing Problem. ISCAS 2007: 2044-2047 - [c130]Haixia Yan, Zhuoyuan Li, Xianlong Hong, Qiang Zhou:
Unified Quadratic Programming Approach For 3-D Mixed Mode Placement. ISCAS 2007: 3411-3414 - [c129]Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu, Bing Lu:
Planar-CRX: A Single-Layer Zero Skew Clock Routing in X-Architecture. ISQED 2007: 299-304 - [c128]Yici Cai, Bin Liu, Jin Shi, Qiang Zhou, Xianlong Hong:
Power Delivery Aware Floorplanning for Voltage Island Designs. ISQED 2007: 350-355 - [c127]Hongjie Bai, Sheqin Dong, Xianlong Hong:
Congestion Driven Buffer Planning for X-Architecture. ISQED 2007: 835-840 - [c126]Liu Yang, Sheqin Dong, Yuchun Ma, Xianlong Hong:
Interconnect Power Optimization Based on Timing Analysis. ISVLSI 2007: 119-124 - [c125]Hailong Yao, Yici Cai, Xianlong Hong:
CMP-aware Maze Routing Algorithm for Yield Enhancement. ISVLSI 2007: 239-244 - [c124]Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu:
Activity-Aware Registers Placement for Low Power Gated Clock Tree Construction. ISVLSI 2007: 383-388 - [c123]Yaoguang Wei, Sheqin Dong, Xianlong Hong, Yuchun Ma:
An accurate and efficient probabilistic congestion estimation model in x architecture. SLIP 2007: 25-32 - 2006
- [j43]Zuying Luo, Yici Cai, Sheldon X.-D. Tan, Xianlong Hong, Xiaoyi Wang, Zhu Pan, Jingjing Fu:
Time-domain analysis methodology for large-scale RLC circuits and its applications. Sci. China Ser. F Inf. Sci. 49(5): 665-680 (2006) - [j42]Jingyu Xu, Xianlong Hong, Tong Jing, Ling Zhang, Jun Gu:
A coupling and crosstalk-considered timing-driven global routing algorithm for high-performance circuit design. Integr. 39(4): 457-473 (2006) - [j41]Yu Hu, Tong Jing, Zhe Feng, Xianlong Hong, Xiaodong Hu, Guiying Yan:
ACO-Steiner: Ant Colony Optimization Based Rectilinear Steiner Minimal Tree Algorithm. J. Comput. Sci. Technol. 21(1): 147-152 (2006) - [j40]Yici Cai, Bin Liu, Yan Xiong, Qiang Zhou, Xianlong Hong:
Priority-Based Routing Resource Assignment Considering Crosstalk. J. Comput. Sci. Technol. 21(6): 913-921 (2006) - [j39]Yuchun Ma, Xianlong Hong, Sheqin Dong, Chung-Kuan Cheng, Jun Gu:
General Floorplans with L/T-Shaped Blocks Using Corner Block List. J. Comput. Sci. Technol. 21(6): 922-926 (2006) - [j38]Hang Li, Jeffrey Fan, Zhenyu Qi, Sheldon X.-D. Tan, Lifeng Wu, Yici Cai, Xianlong Hong:
Partitioning-Based Approach to Fast On-Chip Decoupling Capacitor Budgeting and Minimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(11): 2402-2412 (2006) - [j37]Jingyu Xu, Xianlong Hong, Tong Jing, Yang Yang:
Obstacle-avoiding rectilinear minimum-delay Steiner tree construction toward IP-block-based SOC design. IEEE Trans. Circuits Syst. II Express Briefs 53-II(4): 309-313 (2006) - [j36]Song Chen, Sheqin Dong, Xianlong Hong, Yuchun Ma, Chung-Kuan Cheng:
VLSI Block Placement With Alignment Constraints. IEEE Trans. Circuits Syst. II Express Briefs 53-II(8): 622-626 (2006) - [j35]Yici Cai, Bin Liu, Qiang Zhou, Xianlong Hong:
A Two-Step Heuristic Algorithm for Minimum-Crosstalk Routing Resource Assignment. IEEE Trans. Circuits Syst. II Express Briefs 53-II(10): 1007-1011 (2006) - [j34]Yici Cai, Jingjing Fu, Xianlong Hong, Sheldon X.-D. Tan, Zuying Luo:
Power/Ground Network Optimization Considering Decap Leakage Currents. IEEE Trans. Circuits Syst. II Express Briefs 53-II(10): 1012-1016 (2006) - [j33]Hailong Yao, Yici Cai, Qiang Zhou, Xianlong Hong:
Multilevel Routing With Redundant Via Insertion. IEEE Trans. Circuits Syst. II Express Briefs 53-II(10): 1148-1152 (2006) - [j32]Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Yici Cai, Jinian Bian, Hannah Honghua Yang, Vijay Pitchumani, Chung-Kuan Cheng:
Hierarchical 3-D Floorplanning Algorithm for Wirelength Optimization. IEEE Trans. Circuits Syst. I Regul. Pap. 53-I(12): 2637-2646 (2006) - [j31]Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Jinian Bian, Hannah Honghua Yang, Vijay Pitchumani:
Efficient thermal-oriented 3D floorplanning and thermal via planning for two-stacked-die integration. ACM Trans. Design Autom. Electr. Syst. 11(2): 325-345 (2006) - [j30]Xinjie Wei, Yici Cai, Meng Zhao, Xianlong Hong:
Legitimate Skew Clock Routing with Buffer Insertion. J. VLSI Signal Process. 42(2): 107-116 (2006) - [c122]Liu Yang, Sheqin Dong, Xianlong Hong, Yuchun Ma:
A Two-stage Incremental Floorplanning Algorithm with Boundary Constraints. APCCAS 2006: 792-795 - [c121]Xianlong Hong, Yici Cai, Hailong Yao, Duo Li:
DFM-aware Routing for Yield Enhancement. APCCAS 2006: 1091-1094 - [c120]Qiang Zhou, Yi Zou, Yici Cai, Xianlong Hong:
Variational Circuit Simulator based on a Unified Methodology using Arithmetic over Taylor Polynomials. APCCAS 2006: 1635-1638 - [c119]Bin Liu, Yici Cai, Qiang Zhou, Xianlong Hong:
Power driven placement with layout aware supply voltage assignment for voltage island generation in Dual-Vdd designs. ASP-DAC 2006: 582-587 - [c118]Zhen Cao, Tong Jing, Yu Hu, Yiyu Shi, Xianlong Hong, Xiaodong Hu, Guiying Yan:
DraXRouter: global routing in X-Architecture with dynamic resource assignment. ASP-DAC 2006: 618-623 - [c117]Yiyu Shi, Tong Jing, Lei He,