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ORCIDIntegration, Volume 9
Volume 9, Number 1, February 1990
- Lambert Spaanenburg:
Editorial. 1 - C. C. Su, Majid Sarrafzadeh:
Optimal gate-matrix layout of CMOS functional cells. 3-23 - P. Gee, Min-You Wu, S. M. Kang, Ibrahim N. Hajj:
A metal - metal matrix cell generator for multi-level metal MOS technology. 25-47 - Bruce F. Cockburn, Janusz A. Brzozowski:
Switch-level testability of the dynamic CMOS PLA. 49-80 - Tony M. Carter, Kent F. Smith, Steven R. Jacobs, Richard M. Neff:
Cell matrix methodologies for integrated circuit design. 81-97
Volume 9, Number 2, April 1990
- Lambert Spaanenburg:
Editorial. 107 - Sreejit Chakravarty:
Testing of non-feedback bridging faults. 109-127 - Alan A. Bertossi:
A VLSI system for string matching. 129-139 - Izidor Gertner, Moshe Shamash:
VLSI architectures to compute the Wigner Distribution. 141-161 - Dian Zhou:
An optimum channel routing algorithm in the restricted wire overlap model. 163-177 - Arnold Ginetti, Charles Trullemans:
Compaction of CD(2k - D) control unit architectures. 179-197 - Jingsheng Cong, D. F. Wong
:
Generating more compactable channel routing solutions. 199-214
Volume 9, Number 3, July 1990
- Lambert Spaanenburg:
Editorial. 223 - Sanjay V. Rajopadhye, Richard M. Fujimoto:
Automating the design of systolic arrays. 225-242 - Xianjin Yao, C. L. Liu:
PLA logic minimization by simulated annealing. 243-257 - Youn-Long Lin, Yu-Chin Hsu:
A new algorithm for tile generation. 259-269 - Yeong-Yil Yang, Chong-Min Kyung:
An efficient algorithm for optimal PLA folding. 271-285 - Graham M. Megson, David J. Evans:
The systolic control ring instruction processor (SCRIP). 287-302 - Wei Wang, Craig K. Rushforth:
VLSI implementation of a 16-state coset code. 303-319 - Robert Tjärnström:
Switch-level simulation based on local decisions. 321-338
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