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ORCIDThe Journal of VLSI Signal Processing, Volume 47
Volume 47, Number 1, April 2007
- Gordon J. Brebner
, Samarjit Chakraborty, Weng-Fai Wong:
Editorial for the Special Issue on Field Programmable Technology. 1-2 - Jeffrey M. Arnold:
The Architecture and Development Flow of the S5 Software Configurable Processor. 3-14 - Mateusz Majer, Jürgen Teich, Ali Ahmadinia, Christophe Bobda:
The Erlangen Slot Machine: A Dynamically Reconfigurable FPGA-based Computer. 15-31 - José Gabriel F. Coutinho, M. P. T. Juvonen, J. L. Wang, Benny Lo, Wayne Luk, Oskar Mencer, Guang-Zhong Yang:
Designing a Posture Analysis System with Hardware Implementation. 33-45 - Máire McLoone, Ciaran McIvor:
High-speed & Low Area Hardware Architectures of the Whirlpool Hash Function. 47-57 - Marcio Juliato, Guido Araujo, Julio López, Ricardo Dahab:
A Custom Instruction Approach for Hardware and Software Implementations of Finite Field Arithmetic over F2163 using Gaussian Normal Bases. 59-76 - David B. Thomas, Wayne Luk:
High Quality Uniform Random Number Generation Using LUT Optimised State-transition Matrices. 77-92
Volume 47, Number 2, May 2007
- Roman C. Kordasiewicz, Shahram Shirani:
On Hardware Implementations Of DCT and Quantization Blocks for H.264/AVC. 93-102 - Albert M. K. Cheng, Zhubin Zhang:
Improving Web Server Performance with Adaptive Proxy Caching in Soft Real-time Mobile Applications. 103-115 - Hong Jeong, Yong Kim:
A Systolic Architecture and Implementation of Feedback Network for Blind Source Separation. 117-126 - Andrew Kinane, Noel E. O'Connor:
Energy-efficient Hardware Accelerators for the SA-DCT and Its Inverse. 127-152 - Chun Xue, Zili Shao, Edwin Hsing-Mean Sha:
Maximize Parallelism Minimize Overhead for Nested Loops via Loop Striping. 153-167 - Albert Mo Kim Cheng, Feng Shang:
Priority-driven Coding and Transmission of Progressive JPEG Images for Real-Time Applications. 169-182 - T. Sansaloni, A. Perez-Pascual, Vicente Torres-Carot, Javier Valls:
Scheme for Reducing the Storage Requirements of FFT Twiddle Factors on FPGAs. 183-187
Volume 47, Number 3, June 2007
- Roman C. Kordasiewicz, Shahram Shirani:
On Hardware Implementations Of DCT and Quantization Blocks for H.264/AVC. 189-199 - Sze Wei Lee, Soon-Chieh Lim:
An Enhanced Memory Address Mapping Scheme for Improved Memory Access Performance of 2-D DWT Processing Systems. 201-221 - Wei Han, Kwok-Wai Hon, Cheong-Fat Chan, Oliver Chiu-sing Choy, Kong-Pang Pun:
A Speech Recognition IC Using Hidden Markov Models with Continuous Observation Densities. 223-232 - Jun-Hee Mun, Shung Han Cho, Sangjin Hong:
Flexible Controller Design and Its Application for Concurrent Execution of Buffer Centric Dataflows. 233-257 - Messaoud Ahmed Ouameur, Daniel Massicotte:
Real-time DSP and FPGA Implementation of Wiener LMS Based Multipath Channel Estimation in 3G CDMA Systems. 259-279 - Yi-Hsuan Lee, Cheng Chen:
An Efficient Code Generation Algorithm for Non-orthogonal DSP Architecture. 281-296 - Mame Maria Mbaye, Normand Bélanger, Yvon Savaria, Samuel Pierre:
A Novel Application-specific Instruction-set Processor Design Approach for Video Processing Acceleration. 297-315
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