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ORCIDJean-Loup Baer
- > Home > Persons > Jean-Loup Baer
Publications
- 2003
[c47]Jean-Loup Baer, Douglas Low, Patrick Crowley, Neal Sidhwaney:
Memory Hierarchy Design for a Multiprocessor Look-up Engine. IEEE PACT 2003: 206-216- 2000
- [c45]Wayne A. Wong, Jean-Loup Baer:
Modified LRU Policies for Improving Second-Level Cache Behavior. HPCA 2000: 49-60 - [c44]Patrick Crowley, Marc E. Fiuczynski, Jean-Loup Baer, Brian N. Bershad:
Characterizing processor architectures for programmable network interfaces. ICS 2000: 54-65 - 1999
- [c43]Peter van Vleet, Eric J. Anderson, Lindsay Brown, Jean-Loup Baer, Anna R. Karlin:
Pursuing the Performance Potential of Dynamic Cache Line Sizes. ICCD 1999: 528-537 - [c42]Patrick Crowley, Jean-Loup Baer:
On the Use of Trace Sampling for Architectural Studies of Desktop Applications. SIGMETRICS 1999: 208-209 - 1998
- [c41]Dennis C. Lee, Patrick Crowley, Jean-Loup Baer, Thomas E. Anderson, Brian N. Bershad:
Execution Characteristics of Desktop Applications on Windows NT. ISCA 1998: 27-38 - [c40]Jean-Loup Baer, Wen-Hann Wang:
Retrospective: On the Inclusion Properties for Multi-Level Cache Hierarchies. 25 Years ISCA: Retrospectives and Reprints 1998: 59-60 - [c39]Jean-Loup Baer, Wen-Hann Wang:
On the Inclusion Properties for Multi-Level Cache Hierarchies. 25 Years ISCA: Retrospectives and Reprints 1998: 345-352 - 1996
- [c35]Theodore H. Romer, Dennis Lee, Geoffrey M. Voelker, Alec Wolman, Wayne A. Wong, Jean-Loup Baer, Brian N. Bershad, Henry M. Levy:
The Structure and Performance of Interpreters. ASPLOS 1996: 150-159 - 1995
- [j25]Craig Anderson, Jean-Loup Baer:
Two techniques for improving performance on bus-based multiprocessors. Future Gener. Comput. Syst. 11(6): 537-551 (1995) - [c33]Craig Anderson, Jean-Loup Baer:
Two Techniques for Improving Performance on Bus-Based Multiprocessors. HPCA 1995: 264-275 - [c32]Dennis Lee, Jean-Loup Baer, Brad Calder, Dirk Grunwald:
Instruction Cache Fetch Policies for Speculative Execution. ISCA 1995: 357-367 - 1993
- [c27]Craig Anderson, Jean-Loup Baer:
A Multi-Level Hierarchical Cache Coherence Protocol for Multiprocessors. IPPS 1993: 142-148 - 1992
- [j22]Jonathan Bertoni, Jean-Loup Baer, Wen-Hann Wang:
Scaling shared-bus multiprocessors with multiple buses and shared caches: a performance study. Microprocess. Microsystems 16(7): 339-350 (1992) - 1991
- [j20]Wen-Hann Wang, Jean-Loup Baer:
Efficient Trace-Driven Simulation Methods for Cache Performance Analysis. ACM Trans. Comput. Syst. 9(3): 222-241 (1991) - 1990
- [c20]Wen-Hann Wang, Jean-Loup Baer:
Efficient Trace-Driven Simulation Methods for Cache Performance Analysis. SIGMETRICS 1990: 27-36 - [e2]Jean-Loup Baer, Larry Snyder, James R. Goodman:
Proceedings of the 17th Annual International Symposium on Computer Architecture, Seattle, WA, USA, June 1990. ACM 1990, ISBN 0-89791-366-3 [contents] - 1989
- [j19]Jean-Loup Baer, Wen-Hann Wang:
Multilevel Cache Hierarchies: Organizations, Protocols, and Performance. J. Parallel Distributed Comput. 6(3): 451-476 (1989) - [j18]Jean-Loup Baer, Yi-Bing Lin:
Improving Quicksort Performance with a Codewort Data Structure. IEEE Trans. Software Eng. 15(5): 622-631 (1989) - [c18]Haim E. Mizrahi, Jean-Loup Baer, Edward D. Lazowska, John Zahorjan:
Extending the Memory Hierarchy into Multiprocessor Interconnection Networks: A Performance Analysis. ICPP (1) 1989: 41-50 - [c17]Wen-Hann Wang, Jean-Loup Baer, Henry M. Levy:
Organization and Performance of a Two-Level Virtual-Real Cache Hierarchy. ISCA 1989: 140-148 - [c16]Haim E. Mizrahi, Jean-Loup Baer, Edward D. Lazowska
, John Zahorjan:
Introducing Memory into Switch Elements of Multiprocessor Interconnection Networks. ISCA 1989: 158-166 - 1988
- [c15]Jean-Loup Baer, Meei-Chiueh Liem, Larry McMurchie, Rudolf Nottrott, Lawrence Snyder, Wayne Winder:
A Notation for Describing Multiple Views of VLSI Circuits. DAC 1988: 102-107 - [c14]Jean-Loup Baer, Wen-Hann Wang:
On the Inclusion Properties for Multi-Level Cache Hierarchies. ISCA 1988: 73-80 - 1987
- [c13]Jean-Loup Baer, Wen-Hann Wang:
Architectural Choices for Multi-level Cache Hierarchies. ICPP 1987: 258-261 - 1977
- [j10]Jean-Loup Baer, Carla Schlatter Ellis:
Model, Design, and Evaluation of a Compiler for a Parallel Processing Environment. IEEE Trans. Software Eng. 3(6): 394-405 (1977)
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