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Shlomo Weiss
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Publications
- 2018
- [j41]Ben Perach, Shlomo Weiss:
SiMT-DSP: A Massively Multithreaded DSP Architecture. IEEE Trans. Very Large Scale Integr. Syst. 26(8): 1413-1426 (2018) - 2016
- [j40]Gadi Oxman, Shlomo Weiss:
Deflection Routing in Hierarchical Mesh NoCs. IEEE Embed. Syst. Lett. 8(2): 45-48 (2016) - [j39]Gadi Oxman, Shlomo Weiss:
An NoC Simulator That Supports Deflection Routing, GPU/CPU Integration, and Co-Simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(10): 1667-1680 (2016) - 2015
- [c21]Gadi Oxman, Shlomo Weiss:
DNOC: an accurate and fast virtual channel and deflection routing network-on-chip simulator. ISPASS 2015: 193-202 - 2014
- [j38]Gadi Oxman, Shlomo Weiss:
RIDER: Ring deflection router with buffers. Des. Autom. Embed. Syst. 18(3-4): 141-155 (2014) - [j36]Gadi Oxman, Shlomo Weiss, Yair Be'ery:
Computational methods for Conway's Game of Life cellular automaton. J. Comput. Sci. 5(1): 24-31 (2014) - [j35]Sagi Manole, Amit Golander, Shlomo Weiss:
Protein Sequence Pattern Matching: Leveraging Application Specific Hardware Accelerators. IEEE Trans. Computers 63(2): 448-460 (2014) - [j34]Alexei Jolondz, Shlomo Weiss, Amit Golander:
L1-L2 Interconnect Design Methodology and Arbitration in 3-D IC Multicore Compute Clusters. IEEE Trans. Very Large Scale Integr. Syst. 22(10): 2206-2210 (2014) - 2013
- [j33]Omer Zilberberg, Shlomo Weiss, Sivan Toledo:
Phase-change memory: An architectural perspective. ACM Comput. Surv. 45(3): 29:1-29:33 (2013) - 2012
- [c19]Gadi Oxman, Shlomo Weiss, Yitzhak (Tsahi) Birk:
Streamlined Network-on-Chip for Multicore Embedded Architectures. ARCS 2012: 238-249 - [c18]Gadi Oxman, Shlomo Weiss, Yitzhak (Tsahi) Birk:
Buffered deflection routing for networks-on-chip. INA-OCMC@HiPEAC 2012: 9-12 - 2010
- [j27]Nadav Levison, Shlomo Weiss:
Branch target buffer design for embedded processors. Microprocess. Microsystems 34(6): 215-227 (2010) - [c17]Nadav Levison, Shlomo Weiss:
Low power branch prediction for embedded application processors. ISLPED 2010: 67-72 - 2009
- [j26]Ron Gabor, Avi Mendelson, Shlomo Weiss:
Service level agreement for multithreaded processors. ACM Trans. Archit. Code Optim. 6(2): 6:1-6:33 (2009) - [j25]Amit Golander, Shlomo Weiss:
Checkpoint allocation and release. ACM Trans. Archit. Code Optim. 6(3): 10:1-10:27 (2009) - [j24]Amit Golander, Shlomo Weiss, Ronny Ronen:
Synchronizing Redundant Cores in a Dynamic DMR Multicore Architecture. IEEE Trans. Circuits Syst. II Express Briefs 56-II(6): 474-478 (2009) - [j23]Amit Golander, Shlomo Weiss:
Reexecution and Selective Reuse in Checkpoint Processors. Trans. High Perform. Embed. Archit. Compil. 2: 242-268 (2009) - 2008
- [j22]Amit Golander, Shlomo Weiss, Ronny Ronen:
DDMR: Dynamic and Scalable Dual Modular Redundancy with Short Validation Intervals. IEEE Comput. Archit. Lett. 7(2): 65-68 (2008) - [j20]Amit Golander, Shlomo Weiss:
Hiding the misprediction penalty of a resource-efficient high-performance processor. ACM Trans. Archit. Code Optim. 4(4): 6:1-6:32 (2008) - 2007
- [j19]Ron Gabor, Shlomo Weiss, Avi Mendelson:
Fairness enforcement in switch on event multithreading. ACM Trans. Archit. Code Optim. 4(3): 15 (2007) - 2006
- [c16]Ron Gabor, Shlomo Weiss, Avi Mendelson:
Fairness and Throughput in Switch on Event Multithreading. MICRO 2006: 149-160
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