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Computer Architecture Letters, Volume 7

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Volume 7, Number 1, January - June 2008

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José A. Joao, Onur Mutlu, Hyesoon Kim, Yale N. Patt:
Dynamic Predication of Indirect Jumps. 1-4
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Abhishek Das, Serkan Ozdemir, Gokhan Memik, Joseph Zambreno, Alok N. Choudhary:
Microarchitectures for Managing Chip Revenues under Process Variations. 5-8
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Amir Roth:
Physical Register Reference Counting. 9-12
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José Flich, José Duato:
Logic-Based Distributed Routing for NoCs. 13-16
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Jinhyuk Yoon, Eyee Hyun Nam, Yoon Jae Seong, Hongseok Kim, Bryan Suk Kim, Sang Lyul Min, Yookun Cho:
Chameleon: A High Performance Flash/FRAM Hybrid Solid State Disk Architecture. 17-20
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Arijit Biswas, Paul Racunas, Joel S. Emer, Shubhendu S. Mukherjee:
Computing Accurate AVFs using ACE Analysis on Performance Models: A Rebuttal. 21-24
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Sangyeun Cho, Rami G. Melhem:
Corollaries to Amdahl's Law for Energy. 25-28
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James D. Balfour, William J. Dally, David Black-Schaffer, Vishal Parikh, JongSoo Park:
An Energy-Efficient Processor Architecture for Embedded Systems. 29-32

Volume 7, Number 2, July - December 2008

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Derek Chi-Wai Pao, Wei Lin, Bin Liu:
Pipelined Architecture for Multi-String Matching. 33-36
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Rohit Sunkam Ramanujam, Bill Lin:
Randomized Partially-Minimal Routing on Three-Dimensional Mesh Networks. 37-40
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David Black-Schaffer, James D. Balfour, William J. Dally, Vishal Parikh, JongSoo Park:
Hierarchical Instruction Register Organization. 41-44
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Jaehwan John Lee, Xiang Xiao:
A Parallel Deadlock Detection Algorithm with O(1) Overall Run-time Complexity. 45-48
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Crispín Gómez Requena, Francisco Gilabert Villamón, María Engracia Gómez, Pedro López, José Duato:
Beyond Fat-tree: Unidirectional Load--Balanced Multistage Interconnection Network. 49-52
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Zheng Li, Changyun Zhu, Li Shang, Robert P. Dick, Yihe Sun:
Transaction-Aware Network-on-Chip Resource Reservation. 53-56
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Sevin Fide, Stephen F. Jenks:
Proactive Use of Shared L3 Caches to Enhance Cache Communications in Multi-Core Processors. 57-60
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Isask'har Walter, Israel Cidon, Avinoam Kolodny:
BENoC: A Bus-Enhanced Network on-Chip for a Power Efficient CMP. 61-64
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Amit Golander, Shlomo Weiss, Ronny Ronen:
DDMR: Dynamic and Scalable Dual Modular Redundancy with Short Validation Intervals. 65-68

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