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ORCIDTomohiro Kudoh
- > Home > Persons > Tomohiro Kudoh
Publications
- 2018
[c62]Kazusa Musha
, Tomohiro Kudoh, Hideharu Amano:
Deep Learning on High Performance FPGA Switching Boards: Flow-in-Cloud. ARC 2018: 43-54- 2016
- [j19]Michihiro Koibuchi, Ikki Fujiwara, Kiyo Ishii, Shu Namiki, Fabien Chaix, Hiroki Matsutani, Hideharu Amano, Tomohiro Kudoh:
Optical network technologies for HPC: computer-architects point of view. IEICE Electron. Express 13(6): 20152007 (2016) - [c56]Satoshi Matsuoka, Hideharu Amano, Kengo Nakajima, Koji Inoue, Tomohiro Kudoh, Naoya Maruyama, Kenjiro Taura, Takeshi Iwashita, Takahiro Katagiri, Toshihiro Hanawa, Toshio Endo:
From FLOPS to BYTES: disruptive change in high-performance computing towards the post-moore era. Conf. Computing Frontiers 2016: 274-281 - 2011
- [j13]Michihiro Koibuchi, Tomohiro Otsuka, Tomohiro Kudoh, Hideharu Amano:
A Switch-Tagged Routing Methodology for PC Clusters with VLAN Ethernet. IEEE Trans. Parallel Distributed Syst. 22(2): 217-230 (2011) - 2007
- [j9]Konosuke Watanabe, Tomohiro Otsuka, Junichiro Tsuchiya, Hiroaki Nishi, Junji Yamamoto, Noboru Tanabe, Tomohiro Kudoh, Hideharu Amano:
Martini: A Network Interface Controller Chip for High Performance Computing with Distributed PCs. IEEE Trans. Parallel Distributed Syst. 18(9): 1282-1295 (2007) - 2006
- [c27]Tomohiro Otsuka, Michihiro Koibuchi, Tomohiro Kudoh, Hideharu Amano:
Switch-tagged VLAN Routing Methodology for PC Clusters with Ethernet. ICPP 2006: 479-486 - 2003
- [c22]Tomohiro Otsuka, Konosuke Watanabe, Junichiro Tsuchiya, Hiroshi Harada, Junji Yamamoto, Hiroaki Nishi, Tomohiro Kudoh, Hideharu Amano:
Performance Evaluation of a Prototype of RHiNET-2: A Network-based Distributed Parallel Computing System. Applied Informatics 2003: 738-743 - [c20]Konosuke Watanabe, Tomohiro Otsuka, Junichiro Tsuchiya, Hideharu Amano, Hiroshi Harada, Junji Yamamoto, Hiroaki Nishi, Tomohiro Kudoh:
Performance Evaluation of RHiNET-2/NI: A Network Interface for Distributed Parallel Computing Systems. CCGRID 2003: 318-325 - 2002
- [j7]Noboru Tanabe, Junji Yamamoto, Hiroaki Nishi, Tomohiro Kudoh, Yoshihiro Hamada, Hironori Nakajo, Hideharu Amano:
Low Latency High Bandwidth Message Transfer Mechanisms for a Network Interface Plugged into a Memory Slot. Clust. Comput. 5(1): 7-17 (2002) - [c18]Noboru Tanabe, Yoshihiro Hamada, Hironori Nakajo, Hideki Imashiro, Junji Yamamoto, Tomohiro Kudoh, Hideharu Amano:
Low Latency Communication on DIMMnet-1 Network Interface Plugged into a DIMM Slot. PARELEC 2002: 9-14 - 2001
- [j6]Hiroaki Nishi, Koji Tasho, Tomohiro Kudoh, Hideharu Amano:
A network switch for supporting high-performance parallel processing by computers distributed in local areas. Syst. Comput. Jpn. 32(14): 24-33 (2001) - [c16]Shinji Nishimura, Tomohiro Kudoh, Hiroaki Nishi, Junji Yamamoto, Ryuichiro Ueno, Katsuyoshi Harasawa, Shuji Fukuda, Yasutaka Shikichi, Shigeto Akutsu, Koji Tasho, Hideharu Amano:
RHiNET-3/SW: an 80-Gbit/s high-speed network switch for distributed parallel computing. Hot Interconnects 2001: 119-123 - 2000
- [j5]Shinji Nishimura, Katsuyoshi Harasawa, N. Matsudaira, Shigeto Akutsu, Tomohiro Kudoh, Hiroaki Nishi, Hideharu Amano:
RHiNET-2/SW a Hight-throughput, Compact Network-switch Using 8.8-Gbit/s Optical Interconnection. New Gener. Comput. 18(2): 187-197 (2000) - [c15]Noboru Tanabe, Junji Yamamoto, Hiroaki Nishi, Tomohiro Kudoh, Yoshihiro Hamada, Hironori Nakajo, Hideharu Amano:
MEMOnet : Network interface plugged into a memory slot. CLUSTER 2000: 17-16 - [c14]Hiroaki Nishi, Koji Tasho, Junji Yamamoto, Tomohiro Kudoh, Hideharu Amano:
A Local Area System Network RHinet-1: A Network for High Performance Parallel Computing. HPDC 2000: 296-297 - [c13]Noboru Tanabe, Junji Yamamoto, Hiroaki Nishi, Tomohiro Kudoh, Yoshihiro Hamada, Hironori Nakajo, Hideharu Amano:
On-the-fly Sending: A Low Latency High Bandwidth Message Transfer Mechanism. ISPAN 2000: 186-194 - 1999
- [c12]Xiaoshe Dong, Tomohiro Kudoh, Hideharu Amano:
A Routing Algorithm for DS-WDM Ring. Applied Informatics 1999: 562-565 - 1997
- [c11]Hiroaki Nishi, Hideharu Amano, Katsunobu Nishimura, Kenichiro Anjo, Tomohiro Kudoh:
The RDT network router chip. ASP-DAC 1997: 675-676 - [c10]Akira Funahashi, Toshihiro Hanawa, Hideharu Amano, Tomohiro Kudoh:
Adaptive Routing on the Recursive Diagonal Torus. ISHPC 1997: 171-182 - [c9]Xiaoshe Dong, Tomohiro Kudoh, Hideharu Amano:
Wavelength Division Multiple Access Ring - Virtual Topology on a Simple Ring Network. ISPAN 1997: 30-36 - 1995
- [j4]Takuya Terasawa, Ou Yamamoto, Tomohiro Kudoh, Hideharu Amano:
A Performance Evaluation of the Multiprocessor Testbed ATTEMPT-0. Parallel Comput. 21(5): 701-730 (1995) - [c6]Tomohiro Kudoh, Hideharu Amano, Takashi Matsumoto, Kei Hiraki, Yulu Yang, Katsunobu Nishimura, Koichi Yoshimura, Yasuhito Fukushima:
Hierarchical Bit-Map Directory Schemes on the RDT Interconnection Network for a Massively Parallel Processor JUMP-1. ICPP (1) 1995: 186-193 - 1994
- [c5]Kei Hiraki, Hideharu Amano, Morihiro Kuga, Toshinori Sueyoshi, Tomohiro Kudoh, Hiroshi Nakashima, Hironori Nakajo, Hideo Matsuda, Takashi Matsumoto, Shin-ichiro Mori:
Overview of the JUMP-1, an MPP prototype for general-purpose parallel computations. ISPAN 1994: 427-434 - 1993
- [j3]Tomohiro Kudoh, Tetsuro Kimura, Hideharu Amano, Takuya Terasawa:
A query-based parallel logic simulation algorithm. Syst. Comput. Jpn. 24(2): 11-21 (1993) - 1992
- [c4]Tomohiro Kudoh, Tetsuro Kimura, Hideharu Amano, Takuya Terasawa:
A Parallel Logic Simulation Algorithm Based on Query. ICPP (3) 1992: 262-266 - 1991
- [j2]Taisuke Boku, Tomohiro Kudoh, Hideharu Amano, Tetsuro Kimura:
NCC: A concurrent description language for scientific calculation on multiprocessors. Syst. Comput. Jpn. 22(12): 1-10 (1991) - 1990
- [j1]Hideharu Amano, Taisuke Boku, Tomohiro Kudoh:
(SM)²-II: A Large-Scale Multiprocessor for Sparse Matrix Calculations. IEEE Trans. Computers 39(7): 889-905 (1990) - 1989
- [c3]Hideharu Amano, Takuya Terasawa, Tomohiro Kudoh:
Cache with Synchronization Mechanism. IFIP Congress 1989: 1001-1006 - 1986
- [c2]Chizuko Saito, Hideharu Amano, Tomohiro Kudoh, Hideo Aiso:
An Adaptable Cluster Structure of (SM)²-II. CONPAR 1986: 53-60 - 1985
- [c1]Hideharu Amano, Taisuke Boku, Tomohiro Kudoh, Hideo Aiso:
(SM)²-II: A New Version of the Sparse Matrix Solving Machine. ISCA 1985: 100-107
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