Pei-Wen Luo

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Jwu-E Chen

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Publications

2015
[j6]
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Chien-Chih Huang, Chin-Long Wey, Jwu-E Chen, Pei-Wen Luo:
Performance-Driven Unit-Capacitor Placement of Successive-Approximation-Register ADCs. ACM Trans. Design Autom. Electr. Syst. 21(1): 15:1-15:17 (2015)
2013
[j4]
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  - journals/todaes/HuangWCL13
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Chien-Chih Huang, Chin-Long Wey, Jwu-E Chen, Pei-Wen Luo:
Optimal common-centroid-based unit capacitor placements for yield enhancement of switched-capacitor circuits. ACM Trans. Design Autom. Electr. Syst. 19(1): 7:1-7:13 (2013)
2011
[j3]
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  - journals/ieicet/LuoCW11
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Pei-Wen Luo, Jwu-E Chen, Chin-Long Wey:
Design Methodology for Yield Enhancement of Switched-Capacitor Analog Integrated Circuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 94-A(1): 352-361 (2011)
[c2]
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  - conf/socc/HuangCLW11
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Chien-Chih Huang, Jwu-E Chen, Pei-Wen Luo, Chin-Long Wey:
Yield-award placement optimization for Switched-Capacitor analog integrated circuits. SoCC 2011: 170-173
2010
[j2]
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  - journals/tcad/ChenLW10
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Jwu-E Chen, Pei-Wen Luo, Chin-Long Wey:
Placement Optimization for Yield Improvement of Switched-Capacitor Analog Integrated Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(2): 313-318 (2010)
2009
[c1]
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  - conf/isqed/ChenLW09
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Jwu-E Chen, Pei-Wen Luo, Chin-Long Wey:
Yield evaluation of analog placement with arbitrary capacitor ratio. ISQED 2009: 179-184
2008
[j1]
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  - journals/tcad/LuoCWCCW08
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Pei-Wen Luo, Jwu-E Chen, Chin-Long Wey, Liang-Chia Cheng, Ji-Jan Chen, Wen Ching Wu:
Impact of Capacitance Correlation on Yield Enhancement of Mixed-Signal/Analog Integrated Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(11): 2097-2101 (2008)

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