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ORCIDIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 27
Volume 27, Number 1, January 2008
- Enrico Macii:
Editorial. 1-2 - Andrew B. Kahng, Kambiz Samadi:
CMP Fill Synthesis: A Survey of Recent Studies. 3-19 - Josep Carmona
, Jordi Cortadella:
Encoding Large Asynchronous Controllers With ILP Techniques. 20-33 - Vamsi Vankamamidi, Marco Ottavi, Fabrizio Lombardi:
Two-Dimensional Schemes for Clocking/Timing of QCA Circuits. 34-44 - Shrirang K. Karandikar, Sachin S. Sapatnekar:
Technology Mapping Using Logical Effort for Solving the Load-Distribution Problem. 45-58 - Ting Mei, Jaijeet S. Roychowdhury:
A Time-Domain Oscillator Envelope Tracking Algorithm Employing Dual Phase Conditions. 59-69 - Chris C. N. Chu, Yiu-Chung Wong:
FLUTE: Fast Lookup Table Based Rectilinear Steiner Minimal Tree Algorithm for VLSI Design. 70-83 - Muhammet Mustafa Ozdal, Martin D. F. Wong, Philip S. Honsinger:
Simultaneous Escape-Routing Algorithms for Via Minimization of High-Speed Boards. 84-95 - Amit Kumar, Li Shang, Li-Shiuan Peh, Niraj K. Jha:
System-Level Dynamic Thermal Management for High-Performance Microprocessors. 96-108 - Shankar Mahadevan, Federico Angiolini, Jens Sparsø, Luca Benini, Jan Madsen:
A Reactive and Cycle-True IP Emulator for MPSoC Exploration. 109-122 - Daniel Arumí, Rosa Rodríguez-Montañés, Joan Figueras:
Experimental Characterization of CMOS Interconnect Open Defects. 123-136 - Irith Pomeranz, Sudhakar M. Reddy:
Unspecified Transition Faults: A Transition Fault Model for At-Speed Fault Simulation and Test Generation. 137-146 - Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, Wu-Tung Cheng, Nilanjan Mukherjee, Mark Kassab:
X-Press: Two-Stage X-Tolerant Compactor With Programmable Selector. 147-159 - Jaskirat Singh, Sachin S. Sapatnekar:
A Scalable Statistical Static Timing Analyzer Incorporating Correlated Non-Gaussian and Gaussian Parameter Variations. 160-173 - Saibal Mukhopadhyay, Hamid Mahmoodi, Kaushik Roy:
Reduction of Parametric Failures in Sub-100-nm SRAM Array Using Body Bias. 174-183 - Kai-Hui Chang, Igor L. Markov, Valeria Bertacco:
Fixing Design Errors With Counterexamples and Resynthesis. 184-188 - Sushanta K. Mandal, Shamik Sural, Amit Patra:
ANN- and PSO-Based Synthesis of On-Chip Spiral Inductors for RF ICs. 188-192 - Irith Pomeranz, Sudhakar M. Reddy:
Primary Input Vectors to Avoid in Random Test Sequences for Synchronous Sequential Circuits. 193-197 - Weixin Wu, Michael S. Hsiao:
Mining Global Constraints With Domain Knowledge for Improving Bounded Sequential Equivalence Checking. 197-201
Volume 27, Number 2, February 2008
- Javid Jaffari, Mohab Anis:
Variability-Aware Bulk-MOS Device Design. 205-216 - R. Mahesh, A. Prasad Vinod:
A New Common Subexpression Elimination Algorithm for Realizing Low-Complexity Higher Order Digital Filters. 217-229 - Andrew B. Kahng, Sudhakar Muddu, Puneet Sharma:
Defocus-Aware Leakage Estimation and Control. 230-240 - Ja Chun Ku, Yehea I. Ismail:
Area Optimization for Leakage Reduction and Thermal Stability in Nanometer-Scale Technologies. 241-248 - Ning Dong, Jaijeet S. Roychowdhury:
General-Purpose Nonlinear Model-Order Reduction Using Piecewise-Polynomial Representations. 249-264 - Alexander Heldring, Juan Manuel Rius, José Maria Tamayo, Josep Parrón:
Compressed Block-Decomposition Algorithm for Fast Capacitance Extraction. 265-271 - Ashish Srivastava, Kaviraj Chopra, Saumil Shah, Dennis Sylvester, David T. Blaauw:
A Novel Approach to Perform Gate-Level Yield Analysis and Optimization Considering Correlated Variations in Power and Performance. 272-285 - Tung-Chieh Chen, Yao-Wen Chang, Shyh-Chang Lin:
A New Multilevel Framework for Large-Scale Interconnect-Driven Floorplanning. 286-294 - Jaskirat Singh, Zhi-Quan Luo, Sachin S. Sapatnekar:
A Geometric Programming-Based Worst Case Gate Sizing Method Incorporating Spatial Correlation. 295-308 - Shantanu Dutt, Vinay Verma, Vishal Suthar:
Built-in-Self-Test of FPGAs With Provable Diagnosabilities and High Diagnostic Coverage With Application to Online Testing. 309-326 - Piet Engelke, Ilia Polian, Michel Renovell, Sandip Kundu, Bharath Seshadri, Bernd Becker:
On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing. 327-338 - Haralampos-G. D. Stratigopoulos, Yiorgos Makris:
Error Moderation in Low-Cost Machine-Learning-Based Analog/RF Testing. 339-351 - Zhanglei Wang, Krishnendu Chakrabarty:
Test-Quality/Cost Optimization Using Output-Deviation-Based Reordering of Test Patterns. 352-365 - Himanshu Jain, Daniel Kroening, Natasha Sharygina, Edmund M. Clarke:
Word-Level Predicate-Abstraction and Refinement Techniques for Verifying RTL Verilog. 366-379 - Ilya Wagner, Valeria Bertacco, Todd M. Austin:
Using Field-Repairable Control Logic to Correct Design Errors in Microprocessors. 380-393 - Hiren D. Patel, Sandeep K. Shukla:
On Cosimulating Multiple Abstraction-Level System-Level Models. 394-398 - Irith Pomeranz, Sudhakar M. Reddy:
Scan-Based Delay Test Types and Their Effect on Power Dissipation During Test. 398-403 - Aleksandra Sesic, Stanisa Dautovic, Veljko Malbasa:
Dynamic Power Management of a System With a Two-Priority Request Queue Using Probabilistic-Model Checking. 403-407
Volume 27, Number 3, March 2008
- Sejong Oh, Tag Gon Kim, Jeonghun Cho, Elaheh Bozorgzadeh:
Speculative Loop-Pipelining in Binary Translation for Hardware Acceleration. 409-422 - Andrew C. Ling, Jianwen Zhu, Stephen Dean Brown:
Scalable Synthesis and Clustering Techniques Using Decision Diagrams. 423-435 - Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller, Camille Negrevergne:
Quantum Circuit Simplification and Level Compaction. 436-444 - Sarvesh Bhardwaj, Sarma B. K. Vrudhula:
Leakage Minimization of Digital Circuits Using Gate Sizing in the Presence of Process Variations. 445-455 - Kin Cheong Sou, Alexandre Megretski, Luca Daniel:
A Quasi-Convex Optimization Approach to Parameterized Model Order Reduction. 456-469 - Ngai Wong:
Efficient Positive-Real Balanced Truncation of Symmetric Systems Via Cross-Riccati Equations. 470-480 - Sarvesh H. Kulkarni, Dennis Sylvester, David T. Blaauw:
Design-Time Optimization of Post-Silicon Tuned Circuits Using Adaptive Body Bias. 481-494 - Baolin Yang, Yu Zhu, Ali Bouaricha, Joel R. Phillips:
Applications of the Multi-Interval Chebyshev Collocation Method in RF Circuit Simulation. 495-507 - Peter Hallschmid, Resve A. Saleh:
Fast Design Space Exploration Using Local Regression Modeling With Application to ASIPs. 508-515 - Seda Ogrenci Memik, Rajarshi Mukherjee, Min Ni, Jieyi Long:
Optimizing Thermal Sensor Allocation for Microprocessors. 516-527 - Kubilay Atasu, Can C. Özturan, Günhan Dündar, Oskar Mencer, Wayne Luk:
CHIPS: Custom Hardware Instruction Processor Synthesis. 528-541 - Hristo Nikolov, Todor P. Stefanov, Ed F. Deprettere:
Systematic and Automated Multiprocessor System Design, Programming, and Implementation. 542-555 - Chandan Karfa, Dipankar Sarkar, Chitta Mandal, P. Kumar:
An Equivalence-Checking Method for Scheduling Verification in High-Level Synthesis. 556-569 - Paolo Bernardi, Ernesto Sánchez, Massimiliano Schillaci, Giovanni Squillero, Matteo Sonza Reorda:
An Effective Technique for the Automatic Generation of Diagnosis-Oriented Programs for Processor Cores. 570-574 - Changzhong Chen, Dharmendra Saraswat, Ramachandra Achar, Emad Gad, Michel S. Nakhla, Mustapha Chérif-Eddine Yagoub:
A Robust Algorithm for Passive Reduced-Order Macromodeling of MTLs With FD-PUL Parameters Using Integrated Congruence Transform. 574-578 - Chaeho Chung, Soobum Lee, Byung Man Kwak, Gawon Kim, Joungho Kim:
A Delay Line Circuit Design for Crosstalk Minimization Using Genetic Algorithm. 578-583 - Hangkyu Lee, Irith Pomeranz, Sudhakar M. Reddy:
On Complete Functional Broadside Tests for Transition Faults. 583-587
Volume 27, Number 4, April 2008
- David T. Blaauw, Kaviraj Chopra, Ashish Srivastava, Louis Scheffer:
Statistical Timing Analysis: From Basic Principles to State of the Art. 589-607 - Patrick H. Madden, David Z. Pan:
Guest Editorial. 608-609 - Vishal Khandelwal, Ankur Srivastava:
Variability-Driven Formulation for Simultaneous Gate Sizing and Postsilicon Tunability Allocation. 610-620 - Hua Xiang, Kai-Yuan Chao, Ruchir Puri, Martin D. F. Wong:
Is Your Layout-Density Verification Exact? - A Fast Exact Deep Submicrometer Density Calculation Algorithm. 621-632 - Hua Xiang, Liang Deng, Ruchir Puri, Kai-Yuan Chao, Martin D. F. Wong:
Fast Dummy-Fill Density Analysis With Coupling Constraints. 633-642 - Chung-Wei Lin, Szu-Yu Chen, Chi-Feng Li, Yao-Wen Chang, Chia-Lin Yang:
Obstacle-Avoiding Rectilinear Steiner Tree Construction Based on Spanning Graphs. 643-653 - Tung-Chieh Chen, Yi-Lin Chuang, Yao-Wen Chang:
Effective Wire Models for X-Architecture Placement. 654-658 - Cheoljoo Jeong, Steven M. Nowick:
Technology Mapping and Cell Merger for Asynchronous Threshold Networks. 659-672 - Seok-Won Seong, Prabhat Mishra:
Bitmask-Based Code Compression for Embedded Systems. 673-685 - Ryan Fung, Vaughn Betz, William Chow:
Slack Allocation and Routing to Improve FPGA Timing While Repairing Short-Path Violations. 686-697 - Abusaleh M. Jabir, Dhiraj K. Pradhan, Jimson Mathew:
GfXpress: A Technique for Synthesis and Optimization of GF(2m) Polynomials. 698-711 - Ying Wei, Alex Doboli:
Structural Macromodeling of Analog Circuits Through Model Decoupling and Transformation. 712-725 - Zhen Cao, Tong Jing, Jinjun Xiong, Yu Hu, Zhe Feng, Lei He, Xianlong Hong:
Fashion: A Fast and Accurate Solution to Global Routing Problem. 726-737 - Cheng Zhuo, Jiang Hu, Min Zhao, Kangsheng Chen:
Power Grid Analysis and Optimization Using Algebraic Multigrid. 738-751 - Dmitri Maslov, Sean M. Falconer, Michele Mosca:
Quantum Circuit Placement. 752-763 - Neil Kettle, Andy King:
An Anytime Algorithm for Generalized Symmetry Detection in ROBDDs. 764-777
Volume 27, Number 5, May 2008
- Paolo Maffezzoni:
Unified Computation of Parameter Sensitivity and Signal-Injection Sensitivity in Nonlinear Oscillators. 781-790 - Lihong Zhang, Nuttorn Jangkrajarng, Sambuddha Bhattacharya, Chuanjin Richard Shi:
Parasitic-Aware Optimization and Retargeting of Analog Layouts: A Symbolic-Template Approach. 791-802 - Natasa Miskov-Zivanov, Diana Marculescu:
Modeling and Optimization for Soft-Error Reliability of Sequential Circuits. 803-816 - Shweta Srivastava, Jaijeet S. Roychowdhury:
Independent and Interdependent Latch Setup/Hold Time Characterization via Newton-Raphson Solution and Euler Curve Tracking of State-Transition Equations. 817-830 - Xin Li, Yaping Zhan, Lawrence T. Pileggi:
Quadratic Statistical MAX Approximation for Parametric Yield Estimation of Analog/RF Integrated Circuits. 831-843 - Huang-Yu Chen, Mei-Fang Chiang, Yao-Wen Chang, Lumdo Chen, Brian Han:
Full-Chip Routing Considering Double-Via Insertion. 844-857 - Song Chen, Takeshi Yoshimura:
Fixed-Outline Floorplanning: Block-Position Enumeration and a New Method for Calculating Area Costs. 858-871 - Minsik Cho, Hua Xiang, Ruchir Puri, David Z. Pan:
Track Routing and Optimization for Yield. 872-882 - Bo Hu, Chuanjin Richard Shi:
Simulation of Closely Related Dynamic Nonlinear Systems With Application to Process-Voltage-Temperature Corner Analysis. 883-892 - Diana Marculescu, Siddharth Garg:
Process-Driven Variability Analysis of Single and Multiple Voltage-Frequency Island Latency-Constrained Systems. 893-905 - Claudio Pinello, Luca P. Carloni, Alberto L. Sangiovanni-Vincentelli:
Fault-Tolerant Distributed Deployment of Embedded Control Software. 906-919 - Erkan Acar, Sule Ozev:
Defect-Oriented Testing of RF Circuits. 920-931 - Vishal J. Mehta, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski:
Improving the Resolution of Single-Delay-Fault Diagnosis. 932-945 - Irith Pomeranz, Sudhakar M. Reddy:
On the Saturation of n-Detection Test Generation by Different Definitions With Increased n. 946-957 - Jeong-Ho Han, In-Cheol Park:
FIR Filter Synthesis Considering Multiple Adder Graphs for a Coefficient. 958-962 - Xiaojun Ma, Fabrizio Lombardi:
Synthesis of Tile Sets for DNA Self-Assembly. 963-967 - Bhaskar Pal, Ansuman Banerjee, Arnab Sinha, Pallab Dasgupta:
Accelerating Assertion Coverage With Adaptive Testbenches. 967-972 - Soheil Samii, Mikko Selkälä, Erik Larsson, Krishnendu Chakrabarty, Zebo Peng:
Cycle-Accurate Test Power Modeling and Its Application to SoC Test Architecture Design and Scheduling. 973-977 - Gülin Tulunay, Sina Balkir:
A Synthesis Tool for CMOS RF Low-Noise Amplifiers. 977-982
Volume 27, Number 6, June 2008
- Chong-Fatt Law, Bah-Hwee Gwee, Joseph Sylvester Chang:
Asynchronous Control Network Optimization Using Fast Minimum-Cycle-Time Analysis. 985-998 - Dong Xiang, Yang Zhao, Krishnendu Chakrabarty, Hideo Fujiwara:
A Reconfigurable Scan Architecture With Weighted Scan-Enable Signals for Deterministic BIST. 999-1012 - Levent Aksoy, Eduardo A. C. da Costa, Paulo F. Flores, José Monteiro:
Exact and Approximate Algorithms for the Optimization of Area and Delay in Multiple Constant Multiplications. 1013-1026 - Javid Jaffari, Mohab Anis:
Statistical Thermal Profile Considering Process Variations: Analysis and Applications. 1027-1040 - Xin Li, Jiayong Le, Mustafa Celik, Lawrence T. Pileggi:
Defining Statistical Timing Sensitivity for Logic Circuits With Large-Scale Process and Environmental Variations. 1041-1054 - Zhe-Wei Jiang, Yao-Wen Chang:
An Optimal Network-Flow-Based Simultaneous Diode and Jumper Insertion Algorithm for Antenna Fixing. 1055-1065 - Jarrod A. Roy, Igor L. Markov:
High-Performance Routing at the Nanometer Scale. 1066-1077 - Pramod Chandraiah, Rainer Dömer:
Code and Data Structure Partitioning for Parallel and Flexible MPSoC Specification Using Designer-Controlled Recoding. 1078-1090 - Tarvo Raudvere, Ingo Sander, Axel Jantsch:
Application and Verification of Local Nonsemantic-Preserving Transformations in System Design. 1091-1103 - Wei-Shun Chuang, Shiu-Ting Lin, Wei-Chih Liu, James Chien-Mo Li:
Diagnosis of Multiple Scan Chain Timing Faults. 1104-1116 - S. Saqib Khursheed, Urban Ingelsson, Paul M. Rosinger, Bashir M. Al-Hashimi, Peter Harrod:
Bridging Fault Test Method With Adaptive Power Management Awareness. 1117-1127 - Afshin Abdollahi, Massoud Pedram:
Symmetry Detection and Boolean Matching Utilizing a Signature-Based Canonical Form of Boolean Functions. 1128-1137 - Görschwin Fey, Stefan Staber, Roderick Bloem, Rolf Drechsler:
Automatic Fault Localization for Property Checking. 1138-1149 - Brajesh Kumar Kaushik, Sankar Sarkar:
Crosstalk Analysis for a CMOS-Gate-Driven Coupled Interconnects. 1150-1154 - Sanghyun Park, Aviral Shrivastava, Nikil D. Dutt, Alexandru Nicolau, Yunheung Paek, Eugene Earlie:
Register File Power Reduction Using Bypass Sensitive Compiler. 1155-1159 - Lin Yuan, Gang Qu, Tiziano Villa, Alberto L. Sangiovanni-Vincentelli:
An FSM Reengineering Approach to Sequential Circuit Synthesis by State Splitting. 1159-1164
Volume 27, Number 7, July 2008
- Vijay Victor D'Silva, Daniel Kroening, Georg Weissenbacher:
A Survey of Automated Techniques for Formal Software Verification. 1165-1178 - Rafael Castro-López, Oscar Guerra, Elisenda Roca, Francisco V. Fernández:
An Integrated Layout-Synthesis Approach for Analog ICs. 1179-1189 - Anna Bernasconi, Valentina Ciriani, Rolf Drechsler, Tiziano Villa:
Logic Minimization and Testability of 2-SPP Networks. 1190-1202 - Lei Cheng, Deming Chen, Martin D. F. Wong:
DDBDD: Delay-Driven BDD Synthesis for FPGAs. 1203-1213 - Taehoon Kim, Yungseon Eo:
Analytical CAD Models for the Signal Transients and Crosstalk Noise of Inductance-Effect-Prominent Multicoupled RLC Interconnect Lines. 1214-1227 - Tung-Chieh Chen, Zhe-Wei Jiang, Tien-Chang Hsu, Hsin-Chen Chen, Yao-Wen Chang:
NTUplace3: An Analytical Placer for Large-Scale Mixed-Size Designs With Preplaced Blocks and Density Constraints. 1228-1240 - Andrew B. Kahng, Puneet Sharma, Rasit Onur Topaloglu:
Chip Optimization Through STI-Stress-Aware Placement Perturbations and Fill Insertion. 1241-1252 - Yiyu Shi, Jinjun Xiong, Chunchen Liu, Lei He:
Efficient Decoupling Capacitance Budgeting Considering Operation and Process Variations. 1253-1263 - Soner Yaldiz, Alper Demir, Serdar Tasiran:
Stochastic Modeling and Optimization for Energy Management in Multicore Systems: A Video Decoding Case Study. 1264-1277 - Dariusz Czysz, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer:
Low-Power Test Data Application in EDT Environment Through Decompressor Freeze. 1278-1290 - Sari Onaissi, Farid N. Najm:
A Linear-Time Approach for Static Timing Analysis Covering All Process Corners. 1291-1304 - Daniel Große, Ulrich Kühne, Rolf Drechsler:
Analyzing Functional Coverage in Bounded Model Checking. 1305-1314 - Xiaoxi Xu, Cheng-Chew Lim:
Using Transfer-Resource Graph for Software-Based Verification of System-on-Chip. 1315-1328