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ORCIDACM Transactions on Design Automation of Electronic Systems, Volume 19
Volume 19, Number 1, December 2013
- Raid Ayoub, Rajib Nath, Tajana Simunic Rosing:
CoMETC: Coordinated management of energy/thermal/cooling in servers. 1:1-1:28 - Ra'ed Al-Dujaily, Nizar Dahir
, Terrence S. T. Mak, Fei Xia, Alex Yakovlev:
Dynamic programming-based runtime thermal management (DPRTM): An online thermal control strategy for 3D-NoC systems. 2:1-2:27 - Yen-Jen Chang, Hsiang-Yu Lu:
Improving the performance of port range check for network packet filtering. 3:1-3:21 - Angeliki Kritikakou, Francky Catthoor, Vasilios I. Kelefouras, Costas E. Goutis:
Near-optimal and scalable intrasignal in-place optimization for non-overlapping and irregular access schemes. 4:1-4:30 - Jianhua Li, Liang Shi, Qing'an Li, Chun Jason Xue, Yiran Chen, Yinlong Xu, Wei Wang:
Low-energy volatile STT-RAM cache design using cache-coherence-enabled adaptive refresh. 5:1-5:23 - Xuexin Liu, Sheldon X.-D. Tan, Adolfo Adair Palma-Rodriguez, Esteban Tlelo-Cuautle, Guoyong Shi:
Performance bound analysis of analog circuits in frequency- and time-domain considering process variations. 6:1-6:22 - Chien-Chih Huang, Chin-Long Wey, Jwu-E Chen, Pei-Wen Luo:
Optimal common-centroid-based unit capacitor placements for yield enhancement of switched-capacitor circuits. 7:1-7:13 - Irith Pomeranz:
Built-in generation of multicycle functional broadside tests with observation points. 8:1-8:17 - Jason G. Tong, Marc Boule, Zeljko Zilic:
Test compaction techniques for assertion-based test generation. 9:1-9:29
Volume 19, Number 2, March 2014
- Chia-Heng Tu, Hui-Hsin Hsu, Jen-Hao Chen, Chun-Han Chen, Shih-Hao Hung:
Performance and power profiling for emulated Android systems. 10:1-10:25 - Kunal P. Ganeshpure, Sandip Kundu:
Performance-driven dynamic thermal management of MPSoC based on task rescheduling. 11:1-11:33 - Brett H. Meyer, Adam S. Hartman, Donald E. Thomas:
Cost-effective lifetime and yield optimization for NoC-based MPSoCs. 12:1-12:33 - Jongeun Lee, Seongseok Seo, Jong Kyung Paek, Kiyoung Choi:
Configurable range memory for effective data reuse on programmable accelerators. 13:1-13:22 - Eddie Hung, Steven J. E. Wilton:
Accelerating FPGA debug: Increasing visibility using a runtime reconfigurable observation and triggering network. 14:1-14:23 - Jacopo Panerati, Giovanni Beltrame:
A comparative evaluation of multi-objective exploration algorithms for high-level design. 15:1-15:22 - Seokhyun Lee, Kiyoung Choi:
Critical-path-aware high-level synthesis with distributed controller for fast timing closure. 16:1-16:29 - Yaoguang Wei, Cliff C. N. Sze, Natarajan Viswanathan, Zhuo Li, Charles J. Alpert, Lakshmi N. Reddy, Andrew D. Huber, Gustavo E. Téllez, Douglas Keller, Sachin S. Sapatnekar:
Techniques for scalable and effective routability evaluation. 17:1-17:37 - Irith Pomeranz:
Low-power skewed-load tests based on functional broadside tests. 18:1-18:18 - Irith Pomeranz:
Design-for-testability for multi-cycle broadside tests by holding of state variables. 19:1-19:20 - Sounil Biswas, Hongfei Wang, R. D. (Shawn) Blanton:
Reducing test cost of integrated, heterogeneous systems using pass-fail test data analysis. 20:1-20:23 - Da-Wei Chang, Hsin-Hung Chen, Dau-Jieu Yang, Hsung-Pin Chang:
BLAS: Block-level adaptive striping for solid-state drives. 21:1-21:29
Volume 19, Number 3, June 2014
- Luis Angel D. Bathen, Nikil D. Dutt:
SPMCloud: Towards the Single-Chip Embedded ScratchPad Memory-Based Storage Cloud. 22:1-22:45 - Rafael Rosales, Michael Glaß, Jürgen Teich, Bo Wang, Yang Xu, Ralph Hasholzner:
MAESTRO - Holistic Actor-Oriented Modeling of Nonfunctional Properties and Firmware Behavior for MPSoCs. 23:1-23:26 - Libo Huang, Zhiying Wang, Nong Xiao, Yongwen Wang, Qiang Dou:
Integrated Coherence Prediction: Towards Efficient Cache Coherence on NoC-Based Multicore Architectures. 24:1-24:22 - Po-Chun Huang, Yuan-Hao Chang, Kam-yiu Lam, Jiantao Wang, Chien-Chin Huang:
Garbage Collection for Multiversion Index in Flash-Based Embedded Databases. 25:1-25:27 - Jieun Lim, Nagesh B. Lakshminarayana, Hyesoon Kim, William J. Song, Sudhakar Yalamanchili, Wonyong Sung:
Power Modeling for GPU Architectures Using McPAT. 26:1-26:24 - Chia-Wei Lee, Sun-Yuan Hsieh:
Diagnosability of Component-Composition Graphs in the MM* Model. 27:1-27:14 - Dominik Erb, Michael A. Kochte, Matthias Sauer, Stefan Hillebrecht, Tobias Schubert, Hans-Joachim Wunderlich, Bernd Becker:
Exact Logic and Fault Simulation in Presence of Unknowns. 28:1-28:17 - Jackey Z. Yan, Natarajan Viswanathan, Chris Chu:
An Effective Floorplan-Guided Placement Algorithm for Large-Scale Mixed-Size Designs. 29:1-29:25 - Minseok Kang, Taewhan Kim:
Integrated Resource Allocation and Binding in Clock Mesh Synthesis. 30:1-30:28 - Baktash Boghrati, Sachin S. Sapatnekar:
Incremental Analysis of Power Grids Using Backward Random Walks. 31:1-31:29
Volume 19, Number 4, August 2014
- Reinhard Schneider, Dip Goswami, Samarjit Chakraborty, Unmesh D. Bordoloi, Petru Eles, Zebo Peng:
Quantifying Notions of Extensibility in FlexRay Schedule Synthesis. 32:1-32:37 - Gung-Yu Pan, Jing-Yang Jou, Bo-Cheng Lai:
Scalable Power Management Using Multilevel Reinforcement Learning for Multiprocessors. 33:1-33:23 - Yoon Seok Yang, Reeshav Kumar, Gwan S. Choi, Paul V. Gratz:
WaveSync: Low-Latency Source-Synchronous Bypass Network-on-Chip Architecture. 34:1-34:22 - John Jose, Madhu Mutyam:
Implementation and Analysis of History-Based Output Channel Selection Strategies for Adaptive Routers in Mesh NoCs. 35:1-35:22 - Kun-Lin Tsai, Hao-Tse Chen, Yo-An Lin:
Power and Area Efficiency NoC Router Design for Application-Specific SoC by Using Buffer Merging and Resource Sharing. 36:1-36:21 - Nadereh Hatami, Rafal Baranowski, Paolo Prinetto, Hans-Joachim Wunderlich:
Multilevel Simulation of Nonfunctional Properties by Piecewise Evaluation. 37:1-37:21 - Srivaths Ravi, Michael Joseph:
High-Level Test Synthesis: A Survey from Synthesis Process Flow Perspective. 38:1-38:27 - Da-Cheng Juan, Siddharth Garg, Diana Marculescu:
Statistical Peak Temperature Prediction and Thermal Yield Improvement for 3D Chip Multiprocessors. 39:1-39:23 - Vinicius S. Livramento, Chrystian Guth, José Luís Almada Güntzel, Marcelo O. Johann:
A Hybrid Technique for Discrete Gate Sizing Based on Lagrangian Relaxation. 40:1-40:25 - Yenpo Ho, Garng M. Huang, Peng Li:
Understanding SRAM Stability via Bifurcation Analysis: Analytical Models and Scaling Trends. 41:1-41:25
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