Fule Li

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Meng Ni

> Home > Persons > Fule Li

Publications

2022
[j16]
- view
  authority control:
- export record
  dblp key:
  - journals/tcasI/NiWLRW22
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/tcasI/NiWLRW22
Meng Ni, Xiao Wang, Fule Li, Woogeun Rhee, Zhihua Wang:
A 13-Bit 2-GS/s Time-Interleaved ADC With Improved Correlation-Based Timing Skew Calibration Strategy. IEEE Trans. Circuits Syst. I Regul. Pap. 69(2): 481-494 (2022)
2021
[j15]
- view
  authority control:
- export record
  dblp key:
  - journals/tvlsi/NiWLW21
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/tvlsi/NiWLW21
Meng Ni, Xiao Wang, Fule Li, Zhihua Wang:
A 13-bit 312.5-MS/s Pipelined SAR ADC With Open-Loop Integrator-Based Residue Amplifier and Gain-Stabilized Integration Time Generation. IEEE Trans. Very Large Scale Integr. Syst. 29(7): 1416-1427 (2021)
2020
[c39]
- view
  authority control:
- export record
  dblp key:
  - conf/mwscas/NiWZDLRW20
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/mwscas/NiWZDLRW20
Meng Ni, Xiao Wang, Zhe Zhou, Yang Ding, Fule Li, Woogeun Rhee, Zhihua Wang:
A 13-bit 312.5-MS/s Pipelined SAR ADC with Integrator-type Residue Amplifier and Inter-stage Gain Stabilization Technique. MWSCAS 2020: 341-344
[c38]
- view
  authority control:
- export record
  dblp key:
  - conf/mwscas/NiWZDLRW20a
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/mwscas/NiWZDLRW20a
Meng Ni, Xiao Wang, Zhe Zhou, Yang Ding, Fule Li, Woogeun Rhee, Zhihua Wang:
A Correlation-based Timing Skew Calibration Strategy Using a Time-Interleaved Reference ADC. MWSCAS 2020: 345-348
2015
[c20]
- view
  authority control:
- export record
  dblp key:
  - conf/asicon/NiLLZW15
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/asicon/NiLLZW15
Meng Ni, Fule Li, Weitao Li, Chun Zhang, Zhihua Wang:
A high-speed analog front-end circuit used in a 12bit 1GSps pipeline ADC. ASICON 2015: 1-4

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.