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2000 – 2009
- 2007
[j4]Shoichiro Kawashima, Isao Fukushi, Keizo Morita, Ken-ichi Nakabayashi, Mitsuharu Nakazawa, Kazuaki Yamane, Tomohisa Hirayama, Toru Endo:
A Reliable 1T1C FeRAM Using a Thermal History Tracking 2T2C Dual Reference Level Technique for a Smart Card Application Chip. IEICE Trans. Electron. 90-C(10): 1941-1948 (2007)- 2004
- [j3]Yadollah Eslami, Ali Sheikholeslami, Shoichi Masui, Toru Endo, Shoichiro Kawashima:
Circuit implementations of the differential capacitance read scheme (DCRS) for ferroelectric random-access memories (FeRAM). IEEE J. Solid State Circuits 39(11): 2024-2031 (2004) - 2003
- [j2]Joseph Wai Kit Siu, Yadollah Eslami, Ali Sheikholeslami, P. Glenn Gulak, Toru Endo, Shoichiro Kawashima:
A current-based reference-generation scheme for 1T-1C ferroelectric random-access memories. IEEE J. Solid State Circuits 38(3): 541-549 (2003) - 2002
- [j1]Shoichiro Kawashima, Toru Endo, Akira Yamamoto, Ken-ichi Nakabayashi, Mitsuharu Nakazawa, Keizo Morita, Masaki Aoki:
Bitline GND sensing technique for low-voltage operation FeRAM. IEEE J. Solid State Circuits 37(5): 592-598 (2002) - [c1]Joseph Wai Kit Siu, Yadollah Eslami, Ali Sheikholeslami, P. Glenn Gulak, Toru Endo, Shoichiro Kawashima:
A 16 kb 1T1C FeRAM test chip using current-based reference scheme. CICC 2002: 107-110
Coauthor Index
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