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ORCIDCICC 2002: Orlando, FL, USA
- Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, CICC 2002, Orlando, FL, USA, May 12-15, 2002. IEEE 2002, ISBN 0-7803-7250-6
- Jack Greenbaum:
Reconfigurable logic in SoC systems. 5-8 - Haris Lekatsas, Jörg Henkel, Venkata Jakkula:
1-cycle code decompression circuitry for performance increase of Xtensa-1040-based embedded systems. 9-12 - Michele Borgatti, Francesco Lertora, Benoit Forst, Lorenzo Cali:
A reconfigurable system featuring dynamically extensible embedded microprocessor, FPGA and customisable I/O. 13-16 - Xuejue Huang, Phillip J. Restle, Thomas J. Bucelot, Yu Cao, Tsu-Jae King:
Loop-based interconnect modeling and optimization approach for multi-GHz clock network design. 19-22 - Kanad Chakraborty, David E. Long, John P. Fishburn, Kishore Singhal, Lun Ye, Christopher Ortiz:
A signal integrity-driven buffer insertion technique for post-routing noise and delay optimization. 23-26 - Laurent Lemaitre, Colin C. McAndrew, Steve Hamm:
ADMS-automatic device model synthesizer. 27-30 - Bart De Smedt, Georges G. E. Gielen
:
WATSON: a multi-objective design space exploration tool for analog and RF IC design. 31-34 - Sang-Soo Lee:
Integration and system design trends of ADSL analog front ends and hybrid line interfaces. 37-44 - Tim Piessens, Michiel Steyaert:
A central office combined ADSL-VDSL line driver solution in .35μm CMOS. 45-48 - Hsiang-Hui Chang, Jyh-Woei Lin, Shen-Iuan Liu:
A 6 MHz-130 MHz DLL with a fixed latency of one clock cycle delay. 49-52 - Monte Mar, Bert Sullam, Eric Blom:
An architecture for a programmable mixed-signal device. 55-58 - Ajay Roopchansingh, Jonathan Rose:
Nearest neighbour interconnect architecture in deep submicron FPGAs. 59-62 - Herman Schmit, David Whelihan, Andrew Tsai, Matthew Moe, Benjamin A. Levine, R. Reed Taylor:
PipeRench: A virtualized programmable datapath in 0.18 micron technology. 63-66 - Ernie Lin, Steven J. E. Wilton:
The architecture of dual-mode FPGA embedded system blocks. 67-70 - Marc Boule, Zeljko Zilic:
An FPGA based move generator for the game of chess. 71-74 - Antonio H. Chan, Gordon W. Roberts:
A deep sub-micron timing measurement circuit using a single-stage Vernier delay line. 77-80 - Atila Alvandpour, Ram Krishnamurthy, Shekhar Borkar, A. Rahman, Clair Webb:
A burn-in tolerant dynamic circuit technique. 81-84 - Larry Wissel, Scott Pheasant, Rory Loughran, Chris LeBlanc, Bill Klaasen:
Managing soft errors in ASICs. 85-88 - Chung-Hui Chen, Yean-Kuen Fang, Chien-Chun Tsai, Shen Tu, Mark K. L. Chen, Mi-Chang Chang:
High voltage tolerant ESD design for analog applications in deep submicron CMOS technologies. 89-92 - Jian-Hsing Lee, Yi-Hsun Wu, K. R. Peng, R. Y. Chang, Talee Yu, Tong-Chern Ong:
The embedded SCR NMOS and low capacitance ESD protection device. 93-96 - Pierre C. Fazan, Serguei Okhonin, Mikhail Nagoga, Jean-Michel Sallese:
A simple 1-transistor capacitor-less memory cell for high performance embedded DRAMs. 99-102 - Yoshio Nishida, Wentai Liu:
An interpolating sense circuit for molecular memory. 103-106 - Joseph Wai Kit Siu, Yadollah Eslami, Ali Sheikholeslami, P. Glenn Gulak, Toru Endo, Shoichiro Kawashima:
A 16 kb 1T1C FeRAM test chip using current-based reference scheme. 107-110 - Joong-Seok Moon, William C. Athas, Peter A. Beerel, Jeffrey T. Draper:
Low-power sequential access memory design. 111-114 - Lawrence D. Engh, Albert V. Kordesch, Chun Mai-Liu:
A self adaptive programming method with 5 mV accuracy for multi-level storage in FLASH. 115-118 - Byung-Do Yang, Lee-Sup Kim:
A ROM compression method for continuous data. 119-122 - Ram K. Krishnamurthy, Atila Alvandpour, Vivek De, Shekhar Borkar:
High-performance and low-power challenges for sub-70 nm microprocessor circuits. 125-128 - Motoki Tokumasu, Hiroshige Fujii, Masako Ohta, Tsunealu Fuse, Atsushi Kameyama:
A new reduced clock-swing flip-flop: NAND-type keeper flip-flop (NDKFF). 129-132 - Stephen E. Mick, John M. Wilson, Paul D. Franzon:
4 Gbps high-density AC coupled interconnection. 133-140 - Zhan Yu, Meng-Lin Yu, Kamran Azadet, Alan N. Willson Jr.:
A low power adaptive filter using dynamic reduced 2's-complement representation. 141-144 - Henry Kuo, Ingrid Verbauwhede, Patrick Schaumont:
A 2.29 Gbits/sec, 56 mW non-pipelined Rijndael AES encryption IC in a 1.8 V, 0.18 μm CMOS technology. 147-150 - Yukio Mitsuyama, Zaldy Andales, Takao Onoye, Isao Shirakawa:
Burst mode: a new acceleration mode for 128-bit block ciphers. 151-154 - Katsutoshi Seki, Kousuke Mikami, M. Baba, A. Katayama, H. Tanaka, Y. Hara, M. Kobayashi, N. Okada:
Single-chip FEC codec LSI using iterative CSOC decoder for 10 Gb/s long-haul optical transmission systems. 155-158 - John Redford, Bret Bersack, Matt Monk, Fred Huettig, Dawn Fitzgerald:
A vector DSP for imaging. 159-161 - Shunichi Ishiwata, Tomoo Yamakage, Yoshiro Tsuboi, Takayoshi Shimazawa, Tomoko Kitazawa, Shuji Michinaka, Kunihiko Yahagi, Hideki Takeda, Akihiro Oue, Tomoya Kodama, Nobu Matsumoto, Takayuki Kamei, Takashi Miyamori, Goichi Ootomo, Masataka Matsui:
A single-chip MPEG-2 codec based on customizable media microprocessor. 163-166 - Masayuki Miyama, Osamu Tooyama, N. Takamatsu, T. Kodake, K. Nakamura, A. Kato, Junichi Miyakoshi, K. Hashimoto, Shigenobu Komatsu, M. Yagi, Masao Morimoto, Kazuo Taki, Masahiko Yoshimoto:
An ultra low power, realtime MPEG2 MP@HL motion estimation processor core with SIMD datapath architecture optimized for gradient descent search algorithm. 167-170 - Henri Cloetens, Reinhard Hahn, Bridget Hooser, Frank Lenke:
A low-power highly-integrated MPEG1/2 audio layer 3 (MP3) decoder for CD-based systems. 171-174 - José Silva, Xuesheng Wang, Peter Kiss, Un-Ku Moon, Gabor C. Temes:
Digital techniques for improved ΔΣ data conversion. 183-190 - Matthew R. Miller, Craig S. Petrie:
A multi-bit sigma-delta ADC for multi-mode receivers. 191-194 - Srinivasaraman Chandrasekaran, William C. Black Jr.:
Sub-sampling sigma-delta modulator for baseband processing. 195-198 - M. Jamal Deen, Chih-Hung Chen, Yuhua Cheng:
MOSFET modeling for low noise, RF circuit design. 201-208 - Rainer Kraus, Gerhard Knoblinger:
Modeling the gate-related high-frequency and noise characteristics of deep-submicron MOSFETs. 209-212 - Donhee Ham, Ali Hajimiri:
Virtual damping in oscillators. 213-216 - Yu Cao, Robert A. Groves, Noah Zamdmer, Jean-Olivier Plouchart, Richard A. Wachnik, Xuejue Huang, Tsu-Jae King, Chenming Hu:
Frequency-independent equivalent circuit model for on-chip spiral inductors. 217-220 - Francis M. Rotella, Jeffrey Zachan:
Modeling and optimization of inductors with patterned ground shields for a high performance fully integrated switched tuning VCO. 221-224 - Tajinder Manku, Christopher Snyder, Michele Ting, Yang Ling, Javad Khajehpour, Bill Kung, Lawrence Wong:
Dual mixer downconversion architecture using complex mixing signals: enabling solutions for software defined radios. 227-234 - Peter J. Vancorenland, Philippe Coppejans, Wouter De Cock, Michiel Steyaert:
A quadrature direct digital downconverter. 235-238 - Ranjit Gharpurey, Naveen Yanduru, Francesco Dantoni, Petteri Litmanen, Guglielmo Sirna, Terry Mayhugh Jr., Charles Lin, Irene Yuanying Deng, Paul Fontaine, Fang Lin:
A direct conversion receiver for the 3G WCDMA standard. 239-242 - Danilo Manstretta, Francesco Svelto:
Analysis and optimization of IIP2 in CMOS direct down-converters. 243-246 - Wenjun Sheng, Bo Xia, Ahmed Emira, Chunyu Xin, Sung Tae Moon, Ari Yakov Valero-López, Edgar Sánchez-Sinencio:
A monolithic CMOS low-IF Bluetooth receiver. 247-250 - Mostafa A. I. Elmala, Sherif H. K. Embabi:
A self-calibration technique for mismatches in image-reject receivers. 251-254 - Tetsuro Itakura, Hironori Minamizaki, Tetsuya Saito, Tadashi Kuroda:
A 402-output TFT-LCD driver IC with power-controlling function by selecting number of colors. 257-260 - Koji Fujii, Mamoru Nakanishi, Satoshi Shigematsu, Hiroki Morimura, Takahiro Hatano, Namiko Ikeda, Toshishige Shimamura, Yukio Okazaki, Hakaru Kyuragi:
A 500-dpi cellular-logic processing array for fingerprint-image enhancement and verification. 261-264 - Sung-Hyun Yang, Kyoung-Rok Cho:
High dynamic range CMOS image sensor with conditional reset. 265-268 - Lionel Portmann, Hussein Ballan, Michel J. Declercq:
SOI Hall effect sensor operating up to 270°C. 269-272 - Yi-Cheng Wu, M. Frank Chang:
On-chip RF spiral inductors and bandpass filters using active magnetic energy recovery. 275-278 - Chris DeVries, Ralph Mason:
A 0.18μm CMOS, high Q-enhanced bandpass filter with direct digital tuning. 279-282 - Fikret Duelgel, Edgar Sánchez-Sinencio, Jose Silva-Martinez:
A 2.1GHz 1.3V 5mW programmable Q-enhancement LC bandpass biquad in 0.35μm CMOS. 283-286 - Robert C. Frye, Sharad Kapur, Robert C. Melville:
A 2GHz quadrature hybrid implemented in CMOS technology. 287-290 - Hiroyulu Tsujikawa, Kenji Shimazaki, Shozo Hirano, Motohiro Ohki, Talcashi Yoneda, Hiroshi Benno:
A design methodology for low EMI-noise microprocessor with accurate estimation-reduction-verification. 299-302 - Bernhard Birkl, Bridget Hooser, Marc Janssens, Frank Lenke, Vlado Vorisek:
Design integration, DFT, and verification methodology for an MPEG 1/2 audio layer 3 (MP3) SoC device. 303-306 - Philippe Coussy, Adel Baganne, Eric Martin:
A design methodology for integrating IP into SOC systems. 307-310 - Joseph T. Nabicht, Jeanne K. Pitz, Patrick P. Siniscalchi, Christopher L. Betty, Stephen Maggiotto, Donald Richardson, Stewart M. DeSoto, Sucheendran Sridharan, Sudheer Vemulapalli, Kenneth Downs, D. George Gata, Ali K. Dweik, David Guidry, Kyle D. Muskoff, Brandon Beckham, Glenn H. Westphal:
A voice processing and control module for cable telephony applications. 311-314 - Kenichiro Anjo, Atsushi Okamura, Tomoharu Kajiwarat, Noriko Mizushima, Masafumi Omori, Yasuaki Kuroda:
NECoBus: a high-end SOC bus with a portable and low-latency wrapper-based interface mechanism. 315-318 - Anna Fontanelli, Stefano Arrigoni, Davide Raccagni, Massimo Rosin:
System-on-chip (SoC) requires IC and package co-design and co-verification. 319-322 - Hoi Lee, Philip K. T. Mok:
Active-feedback frequency compensation for low-power multi-stage amplifiers. 325-328 - Xiaohong Peng, Willy Sansen:
Nested feed-forward Gm-stage and ing resistor plus nested-Miller compensation for multistage amplifiers. 329-332 - João Ramos, Michiel Steyaert:
Three stage amplifier with positive feedback compensation scheme. 333-336 - Jie Yan, Randall L. Geiger:
A high gain CMOS operational amplifier with negative conductance gain enhancement. 337-340 - Alireza Zolfaghari, Behzad Razavi:
A noninvasive channel-select filter for a CMOS Bluetooth receiver. 341-344 - Masahiro Murakawa, Toshio Adachi, Yoshihiro Nino, Eiichi Takahashi, Yuji Kasai, Kaoru Takasuka, Tetsuya Higuchi:
An AI-calibrated IF filter: a yield enhancement method with area and power dissipation reductions. 345-348 - H. Yoshizawa, Yochiro Kobayashi, M. Yoshinaga, Y. Ookuma, K. Maio, K. Irikura:
A 1.2 Gbps SOI-BiCMOS write driver for hard disk drives. 349-352 - Tsutomu Yoshimura, Kimio Ueda, Jun Takasoh, Yoshiki Wada, Toshihide Oka, Harufusa Kondoh, Osamu Chiba, Yoshihumi Azekawa, Masahiko Ishiwaki:
A 10Gbase Ethernet transceiver (LAN PHY) in a 1.8 V, 0.18 μm SOI/CMOS technology. 355-358 - Wei-Zen Chen, Chao-Hsin Lu:
A 2.5 Gbps CMOS optical receiver analog front-end. 359-362 - Jeff L. Sonntag, John T. Stonick, James Gorecki, Bill Beale, Bill Check, Xue-Mei Gong, Joe Guiliano, Kyong Lee, Bob Lefferts, David A. Yokoyama-Martin, Un-Ku Moon, Amber Sengir, Stephen Titus, Gu-Yeon Wei, Daniel Weinlader, YaoHua Yang:
An adaptive PAM-4 5 Gb/s backplane transceiver in 0.25 μm CMOS. 363-366 - Behzad Razavi:
The role of monolithic transmission lines in high-speed integrated circuits. 367-374 - Jan-Peter Frambach, Roeland Heijna, Rob Krosschell:
Single reference continuous rate clock and data recovery from 30 Mbit/s to 3.2 Gbit/s. 375-378 - Chris Nicol, Matthew Cooke:
Integrated circuits for 3GPP mobile wireless systems. 381-388 - Alexandre Giulietti, Bruno Bougard, Veerle Derudder, Steven Dupont, Jan-Willem Weijers, Liesbet Van der Perre:
A 80 Mb/s low-power scalable turbo codec core. 389-392 - Tod Wolf, Dale E. Hocevar, Alan Gatherer, Patrick Geremia, Armelle Laine:
600 MHz DSP for baseband processing in 3G base stations. 393-396 - Hiroyuki Igura, Masaru Hirata, Junya Yamada, Masakazu Yamashina, Shigeru Ono:
A low-power W-CDMA demodulator using specially-designed micro-DSPs. 397-400 - Ahmed M. Eltawil, Babak Daneshrad:
Piece-wise parabolic interpolation for direct digital frequency synthesis. 401-404 - Jacob Chang, Srivaths Ravi, Anand Raghunathan:
FLEXBAR: A crossbar switching fabric with improved performance and utilization. 405-408 - Albert Z. Wang, Haigang Feng, Rouying Zhan, Guang Chen, Q. Wu:
ESD protection design for RF integrated circuits: new challenges. 411-418 - David Cassan, John R. Long:
A 1 V 0.9 dB NF low noise amplifier for 5-6 GHz WLAN in 0.18 μm CMOS. 419-422 - Neric H. W. Fong, Jean-Olivier Plouchart, Noah Zamdmer, Duixian Liu, Lawrence F. Wagner, Calvin Plett, Gerry Tarr:
A low-voltage multi-GHz VCO with 58% tuning range in SOI CMOS. 423-426 - Chun-Huat Heng, Bang-Sup Song:
A 1.8 GHz CMOS fractional-N frequency synthesizer with randomized multi-phase VCO. 427-430 - Bang-Sup Song, Thomas Cho, David Kang, Scott Dow:
A 2 MHz GFSK IQ receiver for Bluetooth with DC-tolerant bit slicer. 431-434 - Martin Clara, Andreas Wiesbauer, Franz Kuttner:
A 1.8 V fully embedded 10 b 160 MS/s two-step ADC in 0.18 μm CMOS. 437-440 - Sang-Min Yoo, Tae-Hwan Oh, Jung-Woong Moon, Seung-Hoon Lee, Un-Ku Moon:
A 2.5 V 10 b 120 MSample/s CMOS pipelined ADC with high SFDR. 441-444 - Jan Vandenbussche, Koen Uyttenhove, Erik Lauwers, Michel S. J. Steyaert, Georges G. E. Gielen:
A 8-bit 200 MS/s interpolating/averaging CMOS A/D converter. 445-448 - Patrick G. Drennan, Colin C. McAndrew:
Understanding MOSFET mismatch for analog design. 449-452 - Kannan Krishna, William Bright, D. B. Dye, Khurram Muhammad, Yin Hu:
Spatial averaging and ordering in matched element arrays. 453-456 - Ka Nang Leung, Philip K. T. Mok, Chi Yat Leung:
A 2-V 23-μA 5.3-ppm/°C 4th-order curvature-compensated CMOS bandgap reference. 457-460 - Dong-Young Chang, Lei Wu, Un-Ku Moon:
Low-voltage pipelined ADC using opamp-reset switching technique. 461-464 - Seiichiro Kawamura:
Technology trends and challenges for CMOS/system LSIs for the next 10-15 years. 467-474 - Carlos H. Diaz, Mi-Chang Chang, Tong-Chern Ong, Jack Yuan-Chen Sun:
Application-dependent scaling tradeoffs and optimization in the SoC era. 475-478 - S. L. Lung, Dennis Lin, S. S. Chen, Gary Weng, C. L. Liu, S. C. Lai, C. W. Tsai, T. B. Wu, Rich Liu:
Modularized low temperature LNO/PZT/LNO ferroelectric capacitor-over-interconnect (COI) FeRAM for advanced SOC (ASOC) application. 479-482 - Marko Sokolich:
High speed, low power, optoelectronic InP-based HBT integrated circuits. 483-490 - Muhannad S. Bakir, Hollie A. Reed, Anthony V. Mulé, Paul A. Kohl, Kevin P. Martin, James D. Meindl:
Sea of leads (SoL) characterization and design for compatibility with board-level optical waveguide interconnection. 491-494 - Dicle Ozis, Terri S. Fiez, Kartikeya Mayaram:
A comprehensive geometry-dependent macromodel for substrate noise coupling in heavily doped CMOS processes. 497-500 - Makoto Nagata, Takashi Morie, Atsushi Iwata:
Modeling substrate noise generation in CMOS digital integrated circuits. 501-504 - Nathen Barton, Dicle Ozis, Terri S. Fiez, Kartikeya Mayaram:
The effect of supply and substrate noise on jitter in ring oscillators. 505-508 - Anestis Dounavis, Ramachandra Achar, Michel S. Nakhla:
Passive closed-form time-domain macromodels for on-chip distributed RC interconnects. 509-512 - Rizwan Bashirullah, Wentai Liu, Ralph K. Cavin III:
Delay and power model for current-mode signaling in deep submicron global interconnects. 513-516 - Payam Heydari, Soroush Abbaspour, Massoud Pedram:
A comprehensive study of energy dissipation in lossy transmission lines driven by CMOS inverters. 517-520 - Kazutoshi Kobayashi, Junji Yamaguchi, Hidetoshi Onodera:
Measurement results of on-chip IR-drop. 521-524
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