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2020 – today
- 2020
[j7]Chi-Chang Lu
, Ding-Ke Huang:
A 10-Bits 50-MS/s SAR ADC Based on Area-Efficient and Low-Energy Switching Scheme. IEEE Access 8: 28257-28266 (2020)- [j6]Chang-Chi Lee, Hou-Ming Chen, Chi-Chang Lu, Bo-Yi Lee, Hsien-Chi Huang, He-Sheng Fu, Yong-Xin Lin:
A High-Precision Bandgap Reference With a V-Curve Correction Circuit. IEEE Access 8: 62632-62638 (2020)
2010 – 2019
- 2019
- [j5]Chi-Chang Lu, Ding-Ke Huang:
1.2 V 10-bits 40 MS/s CMOS SAR ADC for low-power applications. IET Circuits Devices Syst. 13(6): 857-862 (2019) - [c16]Chi-Chang Lu, Sheng-Yan Lai:
Capacitive digital-to-analog converter for low-power SAR ADCs. ICCE-TW 2019: 1-2 - 2018
- [c15]Chi-Chang Lu, Chung-Hsien Wu, Hui-Kai Su:
Intelligent Infant Monitoring System Involving a Wi-Fi Wireless Sensor Network. IIH-MSP (2) 2018: 269-276 - 2015
- [c14]Chi-Chang Lu, Po-Hsien Lin:
A Study of the Accessible Approach to Replace the Reservoir Silt Glaze with New Formula. HCI (12) 2015: 83-95 - 2014
- [c13]Chi-Chang Lu, Po-Hsien Lin:
Cultural Creativity in Design Strategy: A Case Study of User's Preference of a Bird-Shaped Teapot. HCI (19) 2014: 775-785 - 2013
- [c12]Chi-Chang Lu, Po-Hsien Lin:
Research on Symbol Expression for Eye Image in Product Design: The Usage of the Chinese Traditional "Yun Wen". HCI (20) 2013: 128-137 - [c11]Chi-Chang Lu:
A 1.2V 10-bit 5 MS/s CMOS cyclic ADC. ISCAS 2013: 1986-1989 - 2011
- [j4]Tsung-Sum Lee, Chi-Chang Lu:
A 330 MHz 11 bit 26.4 mW CMOS Low-Hold-Pedestal Fully Differential Sample-and-Hold Circuit. Circuits Syst. Signal Process. 30(5): 883-898 (2011) - [c10]Chi-Chang Lu, Po-Hsien Lin:
A Study of Producing Ceramic Glaze Utilizing Shihmen Reservoir Silt. HCI (15) 2011: 201-210 - [c9]Po-Hsien Lin, Chi-Chang Lu, Mo-Li Yeh:
Design for Aesthetic Experience. HCI (15) 2011: 322-331 - 2010
- [j3]Tsung-Sum Lee, Chi-Chang Lu:
Two 1-V Fully Differential CMOS Switched-Capacitor Amplifiers. Circuits Syst. Signal Process. 29(2): 195-207 (2010) - [c8]Wei-Chih Chen, Chien-Chun Tsai, Chih-Hsien Chang, Yung-Chow Peng, Fu-Lung Hsueh, Tsung-Hsin Yu, Jinn-Yeh Chien, Wen-Hung Huang, Chi-Chang Lu, Mu-Shan Lin, Chin-Ming Fu, Shu-Chun Yang, Chung-Wing Wong, Wan-Te Chen, Chin-Hua Wen, Li Yueh Wang, Chiang Pu:
A 2.5-8Gb/s transceiver with 5-tap DFE and Second order CDR against 28-inch channel and 5000ppm SSC in 40nm CMOS technology. CICC 2010: 1-4 - [c7]Chi-Chang Lu, Wei-Xiang Tung:
A 1.5V 12-b 40 MSamples/s CMOS pipelined ADC. ISCAS 2010: 4045-4048
2000 – 2009
- 2008
- [c6]Chi-Chang Lu, Wei-Xiang Tung, Chien-Kuo Huang:
A CMOS low-voltage fully differential sample-and-hold circuit. APCCAS 2008: 1188-1191 - 2007
- [j2]Chi-Chang Lu, Tsung-Sum Lee:
A 10-bit 60-MS/s Low-Power CMOS Pipelined Analog-to-Digital Converter. IEEE Trans. Circuits Syst. II Express Briefs 54-II(8): 658-662 (2007) - [c5]Chi-Chang Lu, Jyun-Yi Wu, Tsung-Sum Lee:
A 1.5V 10-b 30-MS/s CMOS Pipelined Analog-to-Digital Converter. ISCAS 2007: 1955-1958 - [c4]Tsung-Sum Lee, Chi-Chang Lu, Jian-Ting Zhan:
A 250MHz 11BIT 20mW low-hold-pedestal CMOS fully differential track-and-hold circuit. SoCC 2007: 47-50 - 2005
- [j1]Tsung-Sum Lee, Chi-Chang Lu:
A 1.5-V 50-MHz pseudodifferential CMOS sample-and-hold circuit with low hold pedestal. IEEE Trans. Circuits Syst. I Regul. Pap. 52-I(9): 1752-1757 (2005) - [c3]Tsung-Sum Lee, Chi-Chang Lu, Shen-Hau Yu, Jian-Ting Zhan:
A very-high-speed low-power low-voltage fully differential CMOS sample-and-hold circuit with low hold pedestal. ISCAS (4) 2005: 3111-3114 - 2003
- [c2]Tsung-Sum Lee, Chi-Chang Lu:
A fully differential low-voltage CMOS high-speed track-and-hold circuit. ISCAS (1) 2003: 397-400 - 2002
- [c1]Tsung-Sum Lee, Chi-Chang Lu:
A low-voltage fully differential CMOS high-speed track-and-hold circuit. APCCAS (1) 2002: 141-144
Coauthor Index
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