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2020 – today
- 2020
[i1]Xiao Yun Xu, Xuan-Lun Huang, Zhan-Ming Li, Jun Gao, Zhi-Qiang Jiao, Yao Wang, Ruo-Jing Ren, H. P. Zhang, Xian-Min Jin:
A Scalable Photonic Computer Solving the Subset Sum Problem. CoRR abs/2002.05108 (2020)
2010 – 2019
- 2015
- [j5]Yu-Yi Chen, Jiun-Lang Huang, Terry Kuo, Xuan-Lun Huang:
Design and Implementation of an FPGA-Based Data/Timing Formatter. J. Electron. Test. 31(5-6): 549-559 (2015) - 2014
- [c11]Chung-Yun Wang, Yu-Yi Chen, Jiun-Lang Huang, Xuan-Lun Huang:
FPGA-Based Subset Sum Delay Lines. ATS 2014: 287-291 - 2013
- [j4]Ming-Feng Huang, Ming-Ching Kuo, Tzu-Yi Yang, Xuan-Lun Huang:
A 58.9-dB ACR, 85.5-dB SBA, 5-26-MHz Configurable-Bandwidth, Charge-Domain Filter in 65-nm CMOS. IEEE J. Solid State Circuits 48(11): 2827-2838 (2013) - [c10]H.-J. Lin, Xuan-Lun Huang, Jiun-Lang Huang:
A mutual characterization based SAR ADC self-testing technique. ETS 2013: 1-6 - [c9]S.-S. Lin, C.-L. Kao, Jiun-Lang Huang, C.-C. Lee, Xuan-Lun Huang:
An IDDQ-based source driver IC design-for-test technique. ICCAD 2013: 393-398 - 2012
- [j3]Xuan-Lun Huang, Jiun-Lang Huang, Hung-I Chen, Chang-Yu Chen, Tseng Kuo-Tsai, Ming-Feng Huang, Yung-Fa Chou, Ding-Ming Kwai:
An MCT-Based Bit-Weight Extraction Technique for Embedded SAR ADC Testing and Calibration. J. Electron. Test. 28(5): 705-722 (2012) - [c8]Y.-H. Chou, Jiun-Lang Huang, Xuan-Lun Huang:
A Built-In Characterization Technique for 1-Bit/Stage Pipelined ADC. Asian Test Symposium 2012: 284-289 - 2011
- [j2]Xuan-Lun Huang, Ping-Ying Kang, Yuan-Chi Yu, Jiun-Lang Huang:
Histogram-Based Calibration of Capacitor Mismatch and Comparator Offset for 1-Bit/Stage Pipelined ADCs. J. Electron. Test. 27(4): 441-453 (2011) - [j1]Xuan-Lun Huang, Jiun-Lang Huang:
ADC/DAC Loopback Linearity Testing by DAC Output Offsetting and Scaling. IEEE Trans. Very Large Scale Integr. Syst. 19(10): 1765-1774 (2011) - [c7]Xuan-Lun Huang, Ping-Ying Kang, Hsiu-Ming Chang, Jiun-Lang Huang, Yung-Fa Chou, Yung-Pin Lee, Ding-Ming Kwai, Cheng-Wen Wu
:
A self-testing and calibration method for embedded successive approximation register ADC. ASP-DAC 2011: 713-718 - [c6]Xuan-Lun Huang, Ping-Ying Kang, Jiun-Lang Huang, Yung-Fa Chou, Yung-Pin Lee, Ding-Ming Kwai:
A Pre- and Post-bond Self-Testing and Calibration Methodology for SAR ADC Array in 3-D CMOS Imager. ETS 2011: 39-44 - 2010
- [c5]Jiun-Lang Huang, Kuo-Yu Chou, Ming-Huan Lu, Xuan-Lun Huang:
A robust ADC code hit counting technique. DATE 2010: 1749-1754 - [c4]Xuan-Lun Huang, Jiun-Lang Huang:
An ADC/DAC loopback testing methodology by DAC output offsetting and scaling. VTS 2010: 289-294
2000 – 2009
- 2009
- [c3]Xuan-Lun Huang, Chen-Yuan Yang, Jiun-Lang Huang:
Diagnosing integrator leakage of single-bit first-order DeltaSigma modulator using DC input. ASP-DAC 2009: 775-780 - [c2]Chen-Yuan Yang, Xuan-Lun Huang, Jiun-Lang Huang:
An On-Chip Integrator Leakage Characterization Technique and Its Application to Switched Capacitor Circuits Testing. Asian Test Symposium 2009: 367-372 - 2006
- [c1]Xuan-Lun Huang, Jiun-Lang Huang:
A routability constrained scan chain ordering technique for test power reduction. ASP-DAC 2006: 648-652
Coauthor Index
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