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ORCIDIEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 19
Volume 19, Number 1, January 2011
- Myint Wai Phyu, Kangkang Fu, Wang Ling Goh, Kiat Seng Yeo
:
Power-Efficient Explicit-Pulsed Dual-Edge Triggered Sense-Amplifier Flip-Flops. 1-9 - Alexandru Andrei, Petru Eles, Olivera Jovanovic, Marcus T. Schmitz, Jens Ogniewski, Zebo Peng:
Quasi-Static Voltage Scaling for Energy Minimization With Time Constraints. 10-23 - Saibal Mukhopadhyay, Rahul M. Rao, Jae-Joon Kim, Ching-Te Chuang:
SRAM Write-Ability Improvement With Transient Negative Bit-Line Voltage. 24-32 - Cheng-Hung Lin, Shih-Chieh Chang:
Efficient Pattern Matching Algorithm for Memory Architecture. 33-41 - Marco D. Santambrogio, Renato Stefanelli:
A New Compact SD2 Positive Integer Triangular Array Division Circuit. 42-51 - Jiun-Ping Wang, Shiann-Rong Kuang, Shish-Chang Liang:
High-Accuracy Fixed-Width Modified Booth Multipliers for Lossy Applications. 52-60 - Joonhee Lee, Sunghyun Park, SeongHwan Cho:
A 470-µW 5-GHz Digitally Controlled Injection-Locked Multi-Modulus Frequency Divider With an In-Phase Dual-Input Injection Scheme. 61-70 - Ian Kuon, Jonathan Rose:
Exploring Area and Delay Tradeoffs in FPGAs With Architecture and Automated Transistor Design. 71-84 - Mehran Mozaffari Kermani, Arash Reyhani-Masoleh:
A Lightweight High-Performance Fault Detection Scheme for the Advanced Encryption Standard Using Composite Fields. 85-91 - Shahin Nazarian, Hanif Fatemi, Massoud Pedram:
Accurate Timing and Noise Analysis of Combinational and Sequential Logic Cells Using Current Source Modeling. 92-103 - Jason Nemeth, Rui Min, Wen-Ben Jone, Yiming Hu:
Location Cache Design and Performance Analysis for Chip Multiprocessors. 104-117 - Chao Shi, Man Kay Law, Amine Bermak:
A Novel Asynchronous Pixel for an Energy Harvesting CMOS Image Sensor. 118-129 - Claude Thibeault, Yassine Hariri:
CDelta IDDQ : Improving Current-Based Testing and Diagnosis Through Modified Test Pattern Generation. 130-141 - Irith Pomeranz, Sudhakar M. Reddy:
Fixed-State Tests for Delay Faults in Scan Designs. 142-146 - Ashoka Visweswara Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino:
Fast Computation of Discharge Current Upper Bounds for Clustered Power Gating. 146-151 - Sherif A. Tawfik, Volkan Kursun:
Multi-Threshold Voltage FinFET Sequential Circuits. 151-156 - Shau-Yu Cheng, Chueh-An Tsai, Terng-Yin Hsu:
Channel Estimator and Aliasing Canceller for Equalizing and Decoding Non-Cyclic Prefixed Single-Carrier Block Transmission via MIMO-OFDM Modem. 156-160 - Minki Cho, Jason Schlessman, Marilyn Wolf, Saibal Mukhopadhyay:
Reconfigurable SRAM Architecture With Spatial Voltage Scaling for Low Power Mobile Multimedia Applications. 161-165 - Hsuan-Jung Hsu, Shi-Yu Huang:
A Low-Jitter ADPLL via a Suppressive Digital Filter and an Interpolation-Based Locking Scheme. 165-170
Volume 19, Number 2, February 2011
- Niraj K. Jha:
Editorial Announcing a New Editor-in-Chief. 173-174 - Tien-Yu Lo, Chung-Chih Hung:
A 1 GHz Equiripple Low-Pass Filter With a High-Speed Automatic Tuning Scheme. 175-181 - Hassan Mostafa, Mohab Anis, Mohamed I. Elmasry:
Analytical Soft Error Models Accounting for Die-to-Die and Within-Die Variations in Sub-Threshold SRAM Cells. 182-195 - Anh-Tuan Do, Zhi-Hui Kong, Kiat Seng Yeo, Jeremy Yung Shern Low:
Design and Sensitivity Analysis of a New Current-Mode Sense Amplifier for Low-Power SRAM. 196-204 - Jongyoon Jung, Taewhan Kim:
Scheduling and Resource Binding Algorithm Considering Timing Variation. 205-216 - Hariharan Sankaran, Srinivas Katkoori:
Simultaneous Scheduling, Allocation, Binding, Re-Ordering, and Encoding for Crosstalk Pattern Minimization During High-Level Synthesis. 217-226 - Jun Seomun, Youngsoo Shin:
Design and Optimization of Power-Gated Circuits With Autonomous Data Retention. 227-236 - Hao Xu, Ranga Vemuri, Wen-Ben Jone:
Dynamic Characteristics of Power Gating During Mode Transition. 237-249 - Yao Guo, Pritish Narayanan, Mahmoud A. Bennaser, Saurabh Chheda, Csaba Andras Moritz:
Energy-Efficient Hardware Data Prefetching. 250-263 - Jae-sun Seo, Himanshu Kaul, Ram Krishnamurthy, Dennis Sylvester, David T. Blaauw:
A Robust Edge Encoding Technique for Energy-Efficient Multi-Cycle Interconnect. 264-273 - Judith Liu-Jimenez, Raul Sánchez-Reillo, Belen Fernandez-Saavedra:
Iris Biometrics for Embedded Systems. 274-282 - Ping Chen, Andy Ye:
The Effect of Multi-Bit Correlation on the Design of Field-Programmable Gate Array Routing Resources. 283-294 - Rakesh Gnana David Jeyasingh, Navakanta Bhat, Bharadwaj S. Amrutur:
Adaptive Keeper Design for Dynamic Logic Circuits Using Rate Sensing Technique. 295-304 - Cheng-Hung Lin, Chun-Yu Chen, An-Yeu Wu:
Area-Efficient Scalable MAP Processor Design for High-Throughput Multistandard Convolutional Turbo Decoding. 305-318 - Ramachandra Achar, Michel S. Nakhla, Harjot S. Dhindsa, Arvind R. Sridhar, Douglas Paul, Natalie Nakhla:
Parallel and Scalable Transient Simulator for Power Grids via Waveform Relaxation (PTS-PWR). 319-332 - Irith Pomeranz, Sudhakar M. Reddy:
Input Necessary Assignments for Testing of Path Delay Faults in Standard-Scan Circuits. 333-337 - Shu-Yi Wong, Chunhong Chen, Q. M. Jonathan Wu:
Low Power Chien Search for BCH Decoder Using RT-Level Power Management. 338-341 - Sourajeet Roy, Anestis Dounavis:
Efficient Delay and Crosstalk Modeling of RLC Interconnects Using Delay Algebraic Equations. 342-346
Volume 19, Number 3, March 2011
- Yehea I. Ismail:
Editorial. 349-368 - Kenneth S. Stevens, Pankaj Golani, Peter A. Beerel:
Energy and Performance Models for Synchronous and Asynchronous Communication. 369-382 - Kevin Brownell, Ali Durlov Khan, Gu-Yeon Wei, David M. Brooks:
Automating Design of Voltage Interpolation to Address Process Variations. 383-396 - Stojan Z. Denic, Bane Vasic, Charalambos D. Charalambous, Jifeng Chen, Janet Meiling Wang:
Information Theoretic Modeling and Analysis for Global Interconnects With Process Variations. 397-410 - Xiaoke Qin, Chetan Muthry, Prabhat Mishra:
Decoding-Aware Compression of FPGA Bitstreams. 411-419 - Costas Argyrides, Dhiraj K. Pradhan, Taskin Koçak:
Matrix Codes for Reliable and Cost Efficient Memory Chips. 420-428 - Sotirios Xydis, George Economakos, Dimitrios Soudris, Kiamal Z. Pekmestzi:
High Performance and Area Efficient Flexible DSP Datapath Synthesis. 429-442 - Debasish Das, Ahmed Shebaita, Hai Zhou, Yehea I. Ismail, Kip Killpack:
FA-STAC: An Algorithmic Framework for Fast and Accurate Coupling Aware Static Timing Analysis. 443-456 - Aida Todri, Malgorzata Marek-Sadowska:
Reliability Analysis and Optimization of Power-Gated ICs. 457-468 - Ashoka Visweswara Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino:
Row-Based Power-Gating: A Novel Sleep Transistor Insertion Methodology for Leakage Power Optimization in Nanometer CMOS Circuits. 469-482 - Wei Xu, Hongbin Sun, Xiaobin Wang, Yiran Chen, Tong Zhang:
Design of Last-Level On-Chip Cache Using Spin-Torque Transfer RAM (STT RAM). 483-493 - Yongho Lee, Deog-Kyoon Jeong, Taewhan Kim:
Comprehensive Analysis and Control of Design Parameters for Power Gated Circuits. 494-498 - Adam B. Kinsman, Nicola Nicolici:
A VLSI Architecture and the FPGA Prototype for MPEG-2 Audio/Video Decoding. 499-503 - Sheng-Chuan Liang, Hao-Chiao Hong:
A Digitally Testable Sigma -Delta Modulator Using the Decorrelating Design-for-Digital-Testability. 503-507 - Yiyu Shi, Jinjun Xiong, Howard Chen, Lei He:
Runtime Resonance Noise Reduction with Current Prediction Enabled Frequency Actuator. 508-512 - Francisco J. Jaime, M. A. Sánchez, Javier Hormigo, Julio Villalba, Emilio L. Zapata:
High-Speed Algorithms and Architectures for Range Reduction Computation. 512-516 - Tai-Hua Lu, Chung-Ho Chen, Kuen-Jong Lee:
Effective Hybrid Test Program Development for Software-Based Self-Testing of Pipeline Processor Cores. 516-520 - Ling Zhang, Yulei Zhang, Hongyu Chen, Bo Yao, Kevin Hamilton, Chung-Kuan Cheng:
On-Chip Interconnect Analysis of Performance and Energy Metrics Under Different Design Goals. 520-524
Volume 19, Number 4, April 2011
- Jae-Sung Yoon, Chang-Hyo Yu, Donghyun Kim, Lee-Sup Kim:
A Dual-Shader 3-D Graphics Processor With Fast 4-D Vector Inner Product Units and Power-Aware Texture Cache. 525-537 - Shoushun Chen, Amine Bermak, Yan Wang:
A CMOS Image Sensor With On-Chip Image Compression Based on Predictive Boundary Adaptation and Memoryless QTD Algorithm. 538-547 - Xuebin Wu, Zhiyuan Yan:
Efficient CODEC Designs for Crosstalk Avoidance Codes Based on Numeral Systems. 548-558 - Ehab Anis Daoud, Nicola Nicolici:
Embedded Debug Architecture for Bypassing Blocking Bugs During Post-Silicon Validation. 559-570 - Fu-Ching Yang, Yi-Ting Lin, Chung-Fu Kao, Ing-Jer Huang:
An On-Chip AHB Bus Tracer With Real-Time Compression and Dynamic Multiresolution Supports for SoC. 571-584 - Tsung-Hsien Lin, Chao-Ching Chi, Wei-Hao Chiu, Yu-Hsiang Huang:
A Synchronous 50% Duty-Cycle Clock Generator in 0.35- μ m CMOS. 585-591 - Shih-Yuan Kao, Shen-Iuan Liu:
A Digitally-Calibrated Phase-Locked Loop With Supply Sensitivity Suppression. 592-602 - Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar:
Adaptive Techniques for Overcoming Performance Degradation Due to Aging in CMOS Circuits. 603-614 - Yu Wang, Xiaoming Chen, Wenping Wang, Yu Cao, Yuan Xie, Huazhong Yang:
Leakage Power and Circuit Aging Cooptimization by Gate Replacement Techniques. 615-628 - Yuejian Wu, Sandy Thomson, Dale Mutcher, Eric Hall:
Built-In Functional Tests for Silicon Validation and System Integration of Telecom SoC Designs. 629-637 - Qiang Zhou, Jin Shi, Bin Liu, Yici Cai:
Floorplanning Considering IR Drop in Multiple Supply Voltages Island Designs. 638-646 - Nauman H. Khan, Syed M. Alam, Soha Hassoun:
Power Delivery Design for 3-D ICs Using Different Through-Silicon Via (TSV) Technologies. 647-658 - Chun-Yu Hsieh, Hong-Wei Huang, Ke-Horng Chen:
A 1-V, 16.9 ppm/ $^{\circ}$ C, 250 nA Switched-Capacitor CMOS Voltage Reference. 659-667 - Young-Hwan Park, Sudeep Pasricha, Fadi J. Kurdahi, Nikil D. Dutt:
A Multi-Granularity Power Modeling Methodology for Embedded Processors. 668-681 - Chong-Fatt Law, Bah-Hwee Gwee, Joseph Sylvester Chang:
Modeling and Synthesis of Asynchronous Pipelines. 682-695 - Inwook Kong, Earl E. Swartzlander Jr.:
A Goldschmidt Division Method With Faster Than Quadratic Convergence. 696-700 - Jaehyouk Choi, Stephen T. Kim, Woonyun Kim, Kwan-Woo Kim, Kyutae Lim, Joy Laskar:
A Low Power and Wide Range Programmable Clock Generator With a High Multiplication Factor. 701-705 - Hsieh-Hung Hsieh, Huan-Sheng Chen, Ping-Hsi Hung, Liang-Hung Lu:
Experimental 5-GHz RF Frontends for Ultra-Low-Voltage and Ultra-Low-Power Operations. 705-709 - Yuan-Ho Chen, Tsin-Yuan Chang, Chung-Yi Li:
High Throughput DA-Based DCT With High Accuracy Error-Compensated Adder Tree. 709-714 - Anita Kumari, Sanjukta Bhanja:
Landauer Clocking for Magnetic Cellular Automata (MCA) Arrays. 714-717 - Mariano Aguirre-Hernandez, Mónico Linares Aranda:
CMOS Full-Adders for Energy-Efficient Arithmetic Applications. 718-721
Volume 19, Number 5, May 2011
- Massimo Alioto, Elio Consoli, Gaetano Palumbo:
Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops: Part I - Methodology and Design Strategies. 725-736 - Massimo Alioto, Elio Consoli, Gaetano Palumbo:
Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops: Part II - Results and Figures of Merit. 737-750 - Massimo Alioto:
Comparative Evaluation of Layout Density in 3T, 4T, and MT FinFET Standard Cells. 751-762 - Hailong Jiao, Volkan Kursun:
Ground Bouncing Noise Suppression Techniques for Data Preserving Sequential MTCMOS Circuits. 763-773 - Renatas Jakushokas, Eby G. Friedman:
Multi-Layer Interdigitated Power Distribution Networks. 774-786 - John Keane, Shrinivas Venkatraman, Paulo F. Butzen, Chris H. Kim:
An Array-Based Test Circuit for Fully Automated Gate Dielectric Breakdown Characterization. 787-795 - Server Kasap, Khaled Benkrid:
High Performance Phylogenetic Analysis With Maximum Parsimony on Reconfigurable Hardware. 796-808 - Subho Chatterjee, Mitchelle Rasquinha, Sudhakar Yalamanchili, Saibal Mukhopadhyay:
A Scalable Design Methodology for Energy Minimization of STTRAM: A Circuit and Architecture Perspective. 809-817 - Woohyung Chun, Sungroh Yoon, Sangjin Hong:
Energy-Aware Interconnect Resource Reduction Through Buffer Access Manipulation for Data-Centric Applications. 818-831 - Jintae Kim, S. Limotyrakis, Chih-Kong Ken Yang:
Multilevel Power Optimization of Pipelined A/D Converters. 832-845 - Jingye Xu, Masud H. Chowdhury:
Fast Waveform Estimation (FWE) for Timing Analysis. 846-856 - Xin Chen, Jun Yang, Longxing Shi:
A Fast Locking All-Digital Phase-Locked Loop via Feed-Forward Compensation Technique. 857-868 - Rajiv V. Joshi, Rouwaida Kanj, Vinod Ramadurai:
A Novel Column-Decoupled 8T Cell for Low-Power Differential and Domino-Based SRAM Design. 869-882 - Mohammad Sharifkhani, Ehsan Rahiminejad, Shah M. Jahinuzzaman, Manoj Sachdev:
A Compact Hybrid Current/Voltage Sense Amplifier With Offset Cancellation for High-Speed SRAMs. 883-894 - Markus Myllylä, Joseph R. Cavallaro, Markku J. Juntti:
Architecture Design and Implementation of the Metric First List Sphere Detector Algorithm. 895-899 - Sheng Lin, Yong-Bin Kim, Fabrizio Lombardi:
A 11-Transistor Nanoscale CMOS Memory Cell for Hardening to Soft Errors. 900-904 - Ren-Jie Lee, Hung-Ming Chen:
Efficient Package Pin-Out Planning With System Interconnects Optimization for Package-Board Codesign. 904-909 - Jiajing Wang, A. Hoefler, Benton H. Calhoun:
An Enhanced Canary-Based System With BIST for SRAM Standby Power Reduction. 909-914 - Peiyi Zhao, Jason McNeely, Weidong Kuang, Nan Wang, Zhongfeng Wang:
Design of Sequential Elements for Low Power Clocking System. 914-918 - Koustav Bhattacharya, N. Ranganathan:
Placement for Immunity of Transient Faults in Cell-Based Design of Nanometer Circuits. 918-923
Volume 19, Number 6, June 2011
- Huang-Chih Kuo, Li-Cian Wu, Hao-Ting Huang, Sheng-Tsung Hsu, Youn-Long Lin:
A Low-Power High-Performance H.264/AVC Intra-Frame Encoder for 1080pHD Video. 925-938 - Chen-Wei Lin, Mango C.-T. Chao, Yen-Shih Huang:
A Novel Pixel Design for AM-OLED Displays Using Nanocrystalline Silicon TFTs. 939-952 - Arindam Basu, Paul E. Hasler:
A Fully Integrated Architecture for Fast and Accurate Programming of Floating Gates Over Six Decades of Current. 953-962 - Satendra Kumar Maurya, Lawrence T. Clark:
A Dynamic Longest Prefix Matching Content Addressable Memory for IP Routing. 963-972 - Jeffrey G. Mueller, Resve A. Saleh:
Autonomous, Multilevel Ring Tuning Scheme for Post-Silicon Active Clock Deskewing Over Intra-Die Variations. 973-986 - Yun Ye, Frank Liu, Min Chen, Sani R. Nassif, Yu Cao:
Statistical Modeling and Simulation of Threshold Variation Under Random Dopant Fluctuations and Line-Edge Roughness. 987-996 - M. Wang, Zili Shao, Jingling Xue:
On Reducing Hidden Redundant Memory Accesses for DSP Applications. 997-1010 - Jia Zhao, Sailaja Madduri, Ramakrishna Vadlamani, Wayne P. Burleson, Russell Tessier:
A Dedicated Monitoring Infrastructure for Multicore Processors. 1011-1022 - Saleh Abdel-Hafeez, Ann Gordon-Ross:
A Digital CMOS Parallel Counter Architecture Based on State Look-Ahead Logic. 1023-1033 - Christos Kyrkou, Theocharis Theocharides:
A Flexible Parallel Hardware Architecture for AdaBoost-Based Real-Time Object Detection. 1034-1047 - Markus Koester, Wayne Luk, Jens Hagemeyer, Mario Porrmann, Ulrich Rückert:
Design Optimizations for Tiled Partially Reconfigurable Systems. 1048-1061 - Giovanni Ansaloni, Paolo Bonzini, Laura Pozzi:
EGRA: A Coarse Grained Reconfigurable Architectural Template. 1062-1074 - Jonathan Rosenfeld, Eby G. Friedman:
A Distributed Filter Within a Switching Converter for Application to 3-D Integrated Circuits. 1075-1085 - Muhammad E. S. Elrabaa:
Robust Two-Phase RZ Asynchronous SoC Interconnects. 1086-1089 - Dimitris Magos, Ioannis Voyiatzis, Steffen Tarnick:
An Accumulator - Based Test-Per-Clock Scheme. 1090-1094 - Irith Pomeranz, Sudhakar M. Reddy:
On Functional Broadside Tests With Functional Propagation Conditions. 1094-1098 - Sangmin Kim, Gerald E. Sobelman, Hanho Lee:
A Reduced-Complexity Architecture for LDPC Layered Decoding Schemes. 1099-1103 - Irith Pomeranz, Sudhakar M. Reddy:
Broadside and Functional Broadside Tests for Partial-Scan Circuits. 1104-1108 - Irith Pomeranz, Sudhakar M. Reddy:
Static Test Data Volume Reduction Using Complementation or Modulo- M Addition. 1108-1112 - Duo Sheng, Ching-Che Chung, Chen-Yi Lee:
A Low-Power and Portable Spread Spectrum Clock Generator for SoC Applications. 1113-1117 - Jing-Hu Li, Xing-Bao Zhang, Ming-Yan Yu:
A 1.2-V Piecewise Curvature-Corrected Bandgap Reference in 0.5 μ m CMOS Process. 1118-1122
Volume 19, Number 7, July 2011
- Hyun Woo Choi, Alfred V. Gomes, Abhijit Chatterjee:
Signal Acquisition of High-Speed Periodic Signals Using Incoherent Sub-Sampling and Back-End Signal Reconstruction Algorithms. 1125-1135 - Atsushi Miyamoto, Naofumi Homma, Takafumi Aoki, Akashi Satoh:
Systematic Design of RSA Processors Based on High-Radix Montgomery Multipliers. 1136-1146 - Marco Bucci, Luca Giancane, Raimondo Luzzi, Giuseppe Scotti, Alessandro Trifiletti:
Delay-Based Dual-Rail Precharge Logic. 1147-1153 - Yulei Zhang, Xiang Hu, Alina Deutsch, A. Ege Engin, James F. Buckwalter, Chung-Kuan Cheng:
Prediction and Comparison of High-Performance On-Chip Global Interconnection. 1154-1166 - Wei-Chih Hsieh, Wei Hwang:
Adaptive Power Control Technique on Power-Gated Circuitries. 1167-1180 - Akhilesh Kumar, Mohab Anis:
IR-Drop Aware Clustering Technique for Robust Power Grid in FPGAs. 1181-1191 - Hao-I Yang, Wei Hwang, Ching-Te Chuang:
Impacts of NBTI/PBTI and Contact Resistance on Power-Gated SRAM With High-kappa Metal-Gate Devices. 1192-1204 - Yamarita Villavicencio, Francesco Musolino, Franco Fiori:
Electrical Model of Microcontrollers for the Prediction of Electromagnetic Emissions. 1205-1217 - Kuo-Hsing Cheng, Kai-Wei Hong, Chi-Hsiang Chen, Jen-Chieh Liu:
A High Precision Fast Locking Arbitrary Duty Cycle Clock Synchronization Circuit. 1218-1228 - Xinmiao Zhang, Fang Cai:
Reduced-Complexity Decoder Architecture for Non-Binary LDPC Codes. 1229-1238 - Yasser Ismail, Mohsen Shaaban, Jason McNeely, Magdy A. Bayoumi:
An Efficient Adaptive High Speed Manipulation Architecture for Fast Variable Padding Frequency Domain Motion Estimation. 1239-1248 - Woohyung Chun, Sungroh Yoon, Sangjin Hong:
Buffer Controller-Based Multiple Processing Element Utilization for Dataflow Synthesis. 1249-1262 - Juan Antonio Clemente, Javier Resano, Carlos González, Daniel Mozos:
A Hardware Implementation of a Run-Time Scheduler for Reconfigurable Systems. 1263-1276 - Shantanu Dutt, Huan Ren:
Discretized Network Flow Techniques for Timing and Wire-Length Driven Incremental Placement With White-Space Satisfaction. 1277-1290 - Huan Ren, Shantanu Dutt:
A Provably High-Probability White-Space Satisfaction Algorithm With Good Performance for Standard-Cell Detailed Placement. 1291-1304 - David C. W. Ng, David K. K. Kwong, Ngai Wong:
A Sub-1 V, 26 muW, Low-Output-Impedance CMOS Bandgap Reference With a Low Dropout or Source Follower Mode. 1305-1309 - Inhwa Jung, Daejung Shin, Taejin Kim, Chulwoo Kim:
A 140 Mb/s to 1.96 Gb/s Referenceless Transceiver With 7.2 µs Frequency Acquisition Time. 1310-1315 - S. Lin, Y.-B. Kim, Fabrizio Lombardi:
Design and Performance Evaluation of Radiation Hardened Latches for Nanoscale CMOS. 1315-1319 - Hao Xu, Wen-Ben Jone, Ranga Vemuri:
Aggressive Runtime Leakage Control Through Adaptive Light-Weight Vth Hopping With Temperature and Process Variation. 1319-1323
Volume 19, Number 8, August 2011
- Kuo-Hsing Cheng, Jen-Chieh Liu, Chih-Yu Chang, Shu-Yu Jiang, Kai-Wei Hong:
Built-in Jitter Measurement Circuit With Calibration Techniques for a 3-GHz Clock Generator. 1325-1335 - Tse-Wei Chen, Shao-Yi Chien:
Flexible Hardware Architecture of Hierarchical K-Means Clustering for Large Cluster Number. 1336-1345 - Yung-Fa Chou, Ding-Ming Kwai, Cheng-Wen Wu:
Yield Enhancement by Bad-Die Recycling and Stacking With Though-Silicon Vias. 1346-1356 - Wei Xu, Tong Zhang:
A Time-Aware Fault Tolerance Scheme to Improve Reliability of Multilevel Phase-Change Memory in the Presence of Significant Resistance Drift. 1357-1367 - Somnath Paul, Swarup Bhunia:
Dynamic Transfer of Computation to Processor Cache for Yield and Reliability Improvement. 1368-1379 - Ho Fai Ko, Adam B. Kinsman, Nicola Nicolici:
Design-for-Debug Architecture for Distributed Embedded Logic Analysis. 1380-1393 - Shota Ishihara, Masanori Hariyama, Michitaka Kameyama:
A Low-Power FPGA Based on Autonomous Fine-Grain Power Gating. 1394-1406 - Kamran Eshraghian, Kyoung-Rok Cho, Omid Kavehei, Soon-Ku Kang, Derek Abbott, Sung-Mo Steve Kang:
Memristor MOS Content Addressable Memory (MCAM): Hybrid Architecture for Future High Performance Search Engines. 1407-1417 - Xin Liu, Yuanjin Zheng, Bin Zhao, Yisheng Wang, Myint Wai Phyu:
An Ultra Low Power Baseband Transceiver IC for Wireless Body Area Network in 0.18-mu m CMOS Technology. 1418-1428 - Ik Joon Chang, Jae-Joon Kim, Keejong Kim, Kaushik Roy:
Robust Level Converter for Sub-Threshold/Super-Threshold Operation: 100 mV to 2.5 V. 1429-1437 - Moo-young Kim, Jinwoo Kim, Tagjong Lee, Chulwoo Kim:
10-bit 100-MS/s Pipelined ADC Using Input-Swapped Opamp Sharing and Self-Calibrated V/I Converter. 1438-1447 - Ming-Chao Tsai, Ting-Chi Wang, Ting Ting Hwang:
Through-Silicon Via Planning in 3-D Floorplanning. 1448-1457 - Selçuk Köse, Emre Salman, Eby G. Friedman:
Shielding Methodologies in the Presence of Power/Ground Noise. 1458-1468 - Mohammad Hosseinabady, Mohammad Reza Kakoee, Jimson Mathew, Dhiraj K. Pradhan:
Low Latency and Energy Efficient Scalable Architecture for Massive NoCs Using Generalized de Bruijn Graph. 1469-1480 - Chua-Chin Wang, Chia-Hao Hsu, Szu-Chia Liao, Yi-Cheng Liu:
A Wide Voltage Range Digital I/O Design Using Novel Floating N-Well Circuit. 1481-1485 - Karim Mohammed, Mohamed Ismail Ali Mohamed, Babak Daneshrad:
A Parameterized Programmable MIMO Decoding Architecture With a Scalable Instruction Set and Compiler. 1485-1489 - Jeonghun Kim, Hanjun Choi, Sungyeal Yoon, Taesik Bang, Jongchan Park, Chaehyun Jung, Jason Cong:
An 8M Polygons/s 3-D Graphics SoC With Full Hardware Geometric and Rendering Engine for Mobile Applications. 1490-1495 - Amirhossein Alimohammad, Saeed Fouladi Fard, Bruce F. Cockburn:
Hardware Implementation of Rayleigh and Ricean Variate Generators. 1495-1499 - Kazeem Alagbe Gbolagade, George Razvan Voicu, Sorin Dan Cotofana:
An Efficient FPGA Design of Residue-to-Binary Converter for the Moduli Set 2n+1, 2n, 2n-1. 1500-1503 - Swaroop Ghosh, Kaushik Roy:
Novel Low Overhead Post-Silicon Self-Correction Technique for Parallel Prefix Adders Using Selective Redundancy and Adaptive Clocking. 1504-1507 - Chester Rebeiro, Sujoy Sinha Roy, Sankara Reddy, Debdeep Mukhopadhyay:
Revisiting the Itoh-Tsujii Inversion Algorithm for FPGA Platforms. 1508-1512 - Jyu-Yuan Lai, Chih-Tsun Huang:
Energy-Adaptive Dual-Field Processor for High-Performance Elliptic Curve Cryptographic Applications. 1512-1517 - Golnar Khodabandehloo, Mitra Mirhassani, Majid Ahmadi:
CVNS-Based Storage and Refreshing Scheme for a Multi-Valued Dynamic Memory. 1517-1521
Volume 19, Number 9, September 2011
- Milin Zhang, Amine Bermak:
Quadrant-Based Online Spatial and Temporal Compressive Acquisition for CMOS Image Sensor. 1525-1534 - Vikram Pudi, K. Sridharan:
Efficient Design of a Hybrid Adder in Quantum-Dot Cellular Automata. 1535-1548 - Tobias Strauch:
Multi-FPGA System With Unlimited and Self-Timed Wave-Pipelined Multiplexed Routing. 1549-1558 - Fang Tang, Amine Bermak:
A 4T Low-Power Linear-Output Current-Mediated CMOS Image Sensor. 1559-1568 - Paolo Magnone, Felice Crupi, Massimo Alioto, Ben Kaczer, Brice De Jaeger:
Understanding the Potential and the Limits of Germanium pMOSFETs for VLSI Circuits From Experimental Measurements. 1569-1582 - John C. Koob, Sue Ann Ung, Bruce F. Cockburn, Duncan G. Elliott:
Design and Characterization of a Multilevel DRAM. 1583-1596 - Avesta Sasan, Houman Homayoun, Ahmed M. Eltawil, Fadi J. Kurdahi:
Inquisitive Defect Cache: A Means of Combating Manufacturing Induced Process Variation. 1597-1609 - Kailash Chandrashekar, Bertan Bakkaloglu:
A 10 b 50 MS/s Opamp-Sharing Pipeline A/D With Current-Reuse OTAs. 1610-1616 - Yufu Zhang, Ankur Srivastava:
Accurate Temperature Estimation Using Noisy Thermal Sensors for Gaussian and Non-Gaussian Cases. 1617-1626 - Guihai Yan, Yinhe Han, Xiaowei Li:
SVFD: A Versatile Online Fault Detection Scheme via Checking of Stability Violation. 1627-1640 - Krutartha Patel, Sri Parameswaran, Roshan G. Ragel:
Architectural Frameworks for Security and Reliability of MPSoCs. 1641-1654 - Qi Wu, Tong Zhang:
Design Techniques to Facilitate Processor Power Delivery in 3-D Processor-DRAM Integrated Systems. 1655-1666 - Rajeev K. Nain, Malgorzata Chrzanowska-Jeske:
Fast Placement-Aware 3-D Floorplanning Using Vertical Constraints on Sequence Pairs. 1667-1680 - Yi-Ying Tsai, Chung-Ho Chen:
Energy-Efficient Trace Reuse Cache for Embedded Processors. 1681-1694 - Naveen Verma:
Analysis Towards Minimization of Total SRAM Energy Over Active and Idle Operating Modes. 1695-1703 - Ahmad Atghiaee, Nasser Masoumi:
A Predictive and Accurate Interconnect Density Function: The Core of a Novel Interconnect-Centric Prediction Engine. 1704-1717 - Won-Joo Yun, Hyun-Woo Lee, Dongsuk Shin, Suki Kim:
A 3.57 Gb/s/pin Low Jitter All-Digital DLL With Dual DCC Circuit for GDDR3 DRAM in 54-nm CMOS Technology. 1718-1722 - Upavan Gupta, Nagarajan Ranganathan:
A Utilitarian Approach to Variation Aware Delay, Power, and Crosstalk Noise Optimization. 1723-1726 - Jaydeep P. Kulkarni, Ashish Goel, Patrick Ndai, Kaushik Roy:
A Read-Disturb-Free, Differential Sensing 1R/1W Port, 8T Bitcell Array. 1727-1730
Volume 19, Number 10, October 2011
- Manas Ranjan Meher, Ching-Chuen Jong, Chip-Hong Chang:
A High Bit Rate Serial-Serial Multiplier With On-the-Fly Accumulation by Asynchronous Counters. 1733-1745 - Luca Henzen, Jean-Philippe Aumasson, Willi Meier, Raphael Chung-Wei Phan:
VLSI Characterization of the Cryptographic Hash Function BLAKE. 1746-1754 - Irith Pomeranz, Sudhakar M. Reddy:
Reducing the Storage Requirements of a Test Sequence by Using One or Two Background Vectors. 1755-1764 - Xuan-Lun Huang, Jiun-Lang Huang:
ADC/DAC Loopback Linearity Testing by DAC Output Offsetting and Scaling. 1765-1774 - Mehdi Baradaran Tahoori:
High Resolution Application Specific Fault Diagnosis of FPGAs. 1775-1786 - Ying Zhang, Huawei Li, Yinghua Min, Xiaowei Li:
Selected Transition Time Adjustment for Tolerating Crosstalk Effects on Network-on-Chip Interconnects. 1787-1800 - Yu Wang, Jiang Xu, Yan Xu, Weichen Liu, Huazhong Yang:
Power Gating Aware Task Scheduling in MPSoC. 1801-1812 - Cathy Qun Xu, Chun Jason Xue, Edwin Hsing-Mean Sha:
Energy-Efficient Joint Scheduling and Application-Specific Interconnection Design. 1813-1822 - Zhuo Feng, Zhiyu Zeng, Peng Li:
Parallel On-Chip Power Distribution Network Analysis on Multi-Core-Multi-GPU Platforms. 1823-1836 - Vinayak Honkote, Baris Taskin:
CROA: Design and Analysis of the Custom Rotary Oscillatory Array. 1837-1847 - Hassan Mostafa, Mohab Anis, Mohamed I. Elmasry:
A Novel Low Area Overhead Direct Adaptive Body Bias (D-ABB) Circuit for Die-to-Die and Within-Die Variations Compensation. 1848-1860 - Gautam Hazari, H. Narayanan:
On the Use of Simple Electrical Circuit Techniques for Performance Modeling and Optimization in VLSI Systems. 1861-1873 - Yu-Shih Su, Da-Chung Wang, Shih-Chieh Chang, Malgorzata Marek-Sadowska:
Performance Optimization Using Variable-Latency Design Style. 1874-1883 - Thidapat Chantem, Xiaobo Sharon Hu, Robert P. Dick:
Temperature-Aware Scheduling and Assignment for Hard Real-Time Applications on MPSoCs. 1884-1897 - Martin Grymel, Steve B. Furber:
A Novel Programmable Parallel CRC Circuit. 1898-1902 - Kiichi Niitsu, Yasufumi Sugimori, Yoshinori Kohama, Kenichi Osada, Naohiko Irie, Hiroki Ishikuro, Tadahiro Kuroda:
Analysis and Techniques for Mitigating Interference From Power/Signal Lines and to SRAM Circuits in CMOS Inductive-Coupling Link for Low-Power 3-D System Integration. 1902-1907 - Irith Pomeranz, Sudhakar M. Reddy:
Test Strength: A Quality Metric for Transition Fault Tests in Full-Scan Circuits. 1907-1911 - Behzad Ebrahimi, Masoud Rostami, Ali Afzali-Kusha, Massoud Pedram:
Statistical Design Optimization of FinFET SRAM Using Back-Gate Voltage. 1911-1916 - Amin Khajeh, Ahmed M. Eltawil, Fadi J. Kurdahi:
Embedded Memories Fault-Tolerant Pre- and Post-Silicon Optimization. 1916-1921 - Lok-Won Kim, John D. Villasenor:
A System-On-Chip Bus Architecture for Thwarting Integrated Circuit Trojan Horses. 1921-1926 - Elham Safi, Andreas Moshovos, Andreas G. Veneris:
Two-Stage, Pipelined Register Renaming. 1926-1931 - Mostafa E. Salehi, Mehrzad Samadi, Mehrdad Najibi, Ali Afzali-Kusha, Massoud Pedram, Sied Mehdi Fakhraie:
Dynamic Voltage and Frequency Scheduling for Embedded Processors Considering Power/Performance Tradeoffs. 1931-1935
Volume 19, Number 11, November 2011
- Chih-Rung Chen, Wei-Su Wong, Ching-Te Chiu:
A 0.64 mm 2 Real-Time Cascade Face Detection Design Based on Reduced Two-Field Extraction. 1937-1948 - Juliana Gjanci, Masud H. Chowdhury:
A Hybrid Scheme for On-Chip Voltage Regulation in System-On-a-Chip (SOC). 1949-1959 - Ajay Taparia, Bhaskar Banerjee, Thayamkulangara R. Viswanathan:
Power-Supply Noise Reduction Using Active Inductors in Mixed-Signal Systems. 1960-1968 - Minjin Zhang, Huawei Li, Xiaowei Li:
Path Delay Test Generation Toward Activation of Worst Case Coupling Effects. 1969-1982 - Tsu-Wei Tseng, Jin-Fu Li:
A Low-Cost Built-In Redundancy-Analysis Scheme for Word-Oriented RAMs With 2-D Redundancy. 1983-1995 - Chengmo Yang, Alex Orailoglu:
Full Fault Resilience and Relaxed Synchronization Requirements at the Cache-Memory Interface. 1996-2009 - Mehdi Modarressi, Arash Tavakkol, Hamid Sarbazi-Azad:
Application-Aware Topology Reconfiguration for On-Chip Networks. 2010-2022 - Sansiri Tanachutiwat, Ming Liu, Wei Wang:
FPGA Based on Integration of CMOS and RRAM. 2023-2032 - Yee Jern Chong, Sri Parameswaran:
Configurable Multimode Embedded Floating-Point Units for FPGAs. 2033-2044 - Debora Matos, Caroline Concatto, Márcio Eduardo Kreutz, Fernanda Lima Kastensmidt, Luigi Carro, Altamiro Amadeu Susin:
Reconfigurable Routers for Low Power and High Performance. 2045-2057 - Kiichi Niitsu, Vishwesh V. Kulkarni, Shinmo Kang, Hiroki Ishikuro, Tadahiro Kuroda:
A 14-GHz AC-Coupled Clock Distribution Scheme With Phase Averaging Technique Using Single LC-VCO and Distributed Phase Interpolators. 2058-2066 - Mathew Paul, Peter Petrov:
Dynamically Adaptive I-Cache Partitioning for Energy-Efficient Embedded Multitasking. 2067-2080 - Houman Homayoun, Avesta Sasan, Jean-Luc Gaudiot, Alexander V. Veidenbaum:
Reducing Power in All Major CAM and SRAM-Based Processor Units via Centralized, Dynamic Resource Size Management. 2081-2094 - Jonathan Rosenfeld, Eby G. Friedman:
Linear and Switch-Mode Conversion in 3-D Circuits. 2095-2108 - Chao Lu, Chi-Ying Tsui, Wing-Hung Ki:
Vibration Energy Scavenging System With Maximum Power Tracking for Micropower Applications. 2109-2119 - Jiajing Wang, Benton H. Calhoun:
Minimum Supply Voltage and Yield Estimation for Large SRAMs Under Parametric Variations. 2120-2125 - Arash Hariri, Arash Reyhani-Masoleh:
Digit-Level Semi-Systolic and Systolic Structures for the Shifted Polynomial Basis Multiplication Over Binary Extension Fields. 2125-2129 - Hassan Mostafa, Mohab Anis, Mohamed I. Elmasry:
A Bias-Dependent Model for the Impact of Process Variations on the SRAM Soft Error Immunity. 2130-2134 - Frank P. Burns, Alexandre V. Bystrov, Albert Koelmans, Alexandre Yakovlev:
Security Evaluation of Balanced 1-of- n Circuits. 2135-2139
Volume 19, Number 12, 2011
- Ajay Taparia, Bhaskar Banerjee, Thayamkulangara R. Viswanathan:
CS-CMOS: A Low-Noise Logic Family for Mixed Signal SoCs. 2141-2148 - Jian Wen Chen, Ruo He Yao, Wei Jing Wu:
Efficient Modulo 2n+1 Multipliers. 2149-2157 - Jin-Fu Lin, Soon-Jyh Chang, Te-Chieh Kung, Hsin-Wen Ting, Chih-Hao Huang:
Transition-Code Based Linearity Test Method for Pipelined ADCs With Digital Error Correction. 2158-2169 - Mango Chia-Tso Chao, Ching-Yu Chin, Yao-Te Tsou, Chi-Min Chang:
A Novel Test Flow for One-Time-Programming Applications of NROM Technology. 2170-2183 - Chin-Lung Su, Rei-Fu Huang, Cheng-Wen Wu, Kun-Lun Luo, Wen Ching Wu:
A Built-in Self-Diagnosis and Repair Design With Fail Pattern Identification for Memories. 2184-2194 - Usman Ahmed, Guy G. Lemieux, Steven J. E. Wilton:
Performance and Cost Tradeoffs in Metal-Programmable Structured ASICs (MPSAs). 2195-2208 - Daniel Arumí, Rosa Rodríguez-Montañés, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman:
Gate Leakage Impact on Full Open Defects in Interconnect Lines. 2209-2220 - Seok-Jae Lee, Ji-Woong Choi, Seon Wook Kim, Jongsun Park:
A Reconfigurable FIR Filter Architecture to Trade Off Filter Performance for Dynamic Power Consumption. 2221-2228 - Joydip Das, Andrew Lam, Steven J. E. Wilton, Philip Heng Wai Leong, Wayne Luk:
An Analytical Model Relating FPGA Architecture to Logic Density and Depth. 2229-2242 - Aida Todri, Malgorzata Marek-Sadowska:
Power Delivery for Multicore Systems. 2243-2255 - Vasilis F. Pavlidis, Ioannis Savidis, Eby G. Friedman:
Clock Distribution Networks in 3-D Integrated Systems. 2256-2266 - Bharadwaj Amrutur, Pratap Kumar Das, Rajath Vasudevamurthy:
0.84 ps Resolution Clock Skew Measurement via Subsampling. 2267-2275 - Zyad Hassan, Nicholas Allec, Fan Yang, Li Shang, Robert P. Dick, Xuan Zeng:
Full-Spectrum Spatial-Temporal Dynamic Thermal Analysis for Nanometer-Scale Integrated Circuits. 2276-2289 - Pei-Yun Tsai, Chung-Yi Lin:
A Generalized Conflict-Free Memory Addressing Scheme for Continuous-Flow Parallel-Processing FFT Processors With Rescheduling. 2290-2302 - Houman Homayoun, Avesta Sasan, Alexander V. Veidenbaum, Hsin-Cheng Yao, Shahin Golshan, Payam Heydari:
MZZ-HVS: Multiple Sleep Modes Zig-Zag Horizontal and Vertical Sleep Transistor Sharing to Reduce Leakage Power in On-Chip SRAM Peripheral Circuits. 2303-2316 - Sun-Mi Park, Ku-Young Chang:
Fast Bit-Parallel Shifted Polynomial Basis Multiplier Using Weakly Dual Basis Over GF(2m). 2317-2321 - Martin Omaña, Cecilia Metra, T. M. Mak, Simon Tam:
Low-Cost Dynamic Compensation Scheme for Local Clocks of Next Generation High Performance Microprocessors. 2322-2325 - Roberto Gutiérrez, Javier Valls:
Low Cost Hardware Implementation of Logarithm Approximation. 2326-2330 - Xrysovalantis Kavousianos, Vasileios Tenentes, Krishnendu Chakrabarty, Emmanouil Kalligeros:
Defect-Oriented LFSR Reseeding to Target Unmodeled Defects Using Stuck-at Test Sets. 2330-2335 - Shibaji Banerjee, Jimson Mathew, Dhiraj K. Pradhan, Bhargab B. Bhattacharya, Saraju P. Mohanty:
A Routing-Aware ILS Design Technique. 2335-2338 - David Kidd, Keven Dunn, Steve Nishimoto, Lief O'Donnell, Daniel Rodriguez:
High Productivity Circuit Methodology for a Semi-Custom Embedded Processor. 2339-2342
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