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ORCIDJosé González 0002
Person information
- affiliation: Intel Labs, Intel Barcelona Research Center, Spain
- affiliation (former): University of Murcia, Spain
- affiliation (former): Technical University of Valencia, Spain
Other persons with the same name
- José González — disambiguation page
- José González 0001
![[0000-0002-3448-7393]](https://dblp.dagstuhl.de/img/orcid-mark.12x12.png "0000-0002-3448-7393")
(aka: José González-Vargas) — Consejo Superior de Investigaciones Cientificas, Instituto Cajal, Madrid, Spain - José R. González (aka: José Ramón González Montero, José González 0003) — Federal Fluminense University, Rio de Janeiro, Brazil
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2010 – 2019
- 2013
[j16]Enric Herrero, José González, Ramon Canal, Dean M. Tullsen:
Thread Row Buffers: Improving Memory Performance Isolation and Throughput in Multiprogrammed Environments. IEEE Trans. Computers 62(9): 1879-1892 (2013)- 2012
- [j15]Enric Herrero, José González, Ramon Canal:
Distributed Cooperative Caching: An Energy Efficient Memory Scheme for Chip Multiprocessors. IEEE Trans. Parallel Distributed Syst. 23(5): 853-861 (2012) - 2011
- [j14]Fernando Latorre, Grigorios Magklis, José González, Pedro Chaparro, Antonio González:
CROB: Implementing a Large Instruction Window through Compression. Trans. High Perform. Embed. Archit. Compil. 3: 115-134 (2011) - [c41]Qiong Cai, José González, Grigorios Magklis, Pedro Chaparro, Antonio González:
Thread shuffling: combining DVFS and thread migration toreduce energy consumptions for multi-core systems. ISLPED 2011: 379-384 - 2010
- [j13]Ryan N. Rakvic, José González, Qiong Cai, Pedro Chaparro, Grigorios Magklis, Antonio González:
Energy efficiency via thread fusion and value reuse. IET Comput. Digit. Tech. 4(2): 114-125 (2010) - [j12]Ryan N. Rakvic, Qiong Cai, José González, Grigorios Magklis, Pedro Chaparro, Antonio González:
Thread-management techniques to maximize efficiency in multicore and simultaneous multithreaded microprocessors. ACM Trans. Archit. Code Optim. 7(2): 9:1-9:25 (2010) - [c40]Enric Herrero, José González, Ramon Canal:
Power-Efficient Spilling Techniques for Chip Multiprocessors. Euro-Par (1) 2010: 256-267 - [c39]Enric Herrero, José González, Ramon Canal:
Elastic cooperative caching: an autonomous dynamically adaptive memory hierarchy for chip multiprocessors. ISCA 2010: 419-428
2000 – 2009
- 2009
- [j11]Gregorio Bernabé, José M. García, José González:
A lossy 3D wavelet transform for high-quality compression of medical video. J. Syst. Softw. 82(3): 526-534 (2009) - [c38]Pedro Chaparro, José González, Qiong Cai, Greg Chrysler:
Dynamic thermal management using thin-film thermoelectric cooling. ISLPED 2009: 111-116 - 2008
- [c37]Enric Herrero, José González, Ramon Canal:
Distributed cooperative caching. PACT 2008: 134-143 - [c36]Qiong Cai, José González, Ryan N. Rakvic, Grigorios Magklis, Pedro Chaparro, Antonio González:
Meeting points: using thread criticality to adapt multicore hardware to parallel regions. PACT 2008: 240-249 - [c35]Qiong Cai, Josep M. Codina, José González, Antonio González:
A software-hardware hybrid steering mechanism for clustered microarchitectures. IPDPS 2008: 1-12 - [c34]Fernando Latorre, José González, Antonio González:
Efficient resources assignment schemes for clustered multithreaded processors. IPDPS 2008: 1-12 - [c33]José González, Qiong Cai, Pedro Chaparro, Grigorios Magklis, Ryan N. Rakvic, Antonio González:
Thread fusion. ISLPED 2008: 363-368 - 2007
- [j10]Gregorio Bernabé, Ricardo Fernández Pascual, José M. García, Manuel E. Acacio, José González:
An efficient implementation of a 3D wavelet transform based encoder on hyper-threading technology. Parallel Comput. 33(1): 54-72 (2007) - [j9]Pedro Chaparro, José González, Grigorios Magklis, Qiong Cai, Antonio González:
Understanding the Thermal Implications of Multi-Core Architectures. IEEE Trans. Parallel Distributed Syst. 18(8): 1055-1065 (2007) - [c32]Fernando Latorre, Grigorios Magklis, José González, Pedro Chaparro, Antonio González:
Building a large instruction window through ROB compression. MEDEA@PACT 2007: 41-48 - 2006
- [c31]Grigorios Magklis, Pedro Chaparro, José González, Antonio González:
Independent front-end and back-end dynamic voltage scaling for a GALS microarchitecture. ISLPED 2006: 49-54 - 2005
- [j8]Manuel E. Acacio, José González, José M. García, José Duato:
A Two-Level Directory Architecture for Highly Scalable cc-NUMA Multiprocessors. IEEE Trans. Parallel Distributed Syst. 16(1): 67-79 (2005) - [j7]Gregorio Bernabé, José M. García, José González:
Reducing 3D Fast Wavelet Transform Execution Time Using Blocking and the Streaming SIMD Extensions. J. VLSI Signal Process. 41(2): 209-223 (2005) - [c30]Pedro Chaparro, Grigorios Magklis, José González, Antonio González:
Distributing the Frontend for Temperature Reduction. HPCA 2005: 61-70 - 2004
- [j6]Javier Cuenca, Domingo Giménez, José González:
Architecture of an automatically tuned linear algebra library. Parallel Comput. 30(2): 187-210 (2004) - [j5]Teresa Monreal, Víctor Viñals, José González, Antonio González, Mateo Valero:
Late Allocation and Early Release of Physical Registers. IEEE Trans. Computers 53(10): 1244-1259 (2004) - [j4]Manuel E. Acacio, José González, José M. García, José Duato:
An Architecture for High-Performance Scalable Shared-Memory Multiprocessors Exploiting On-Chip Integration. IEEE Trans. Parallel Distributed Syst. 15(8): 755-768 (2004) - [c29]Pedro Chaparro, José González, Antonio González:
Thermal-Aware Clustered Microarchitectures. ICCD 2004: 48-53 - [c28]Grigorios Magklis, José González, Antonio González:
Frontend Frequency-Voltage Adaptation for Optimal Energy-Delay^2. ICCD 2004: 250-255 - [c27]Fernando Latorre, José González, Antonio González:
Back-end assignment schemes for clustered multithreaded processors. ICS 2004: 316-325 - [c26]José González, Fernando Latorre, Antonio González:
Cache organizations for clustered microarchitectures. WMPI 2004: 46-55 - 2003
- [c25]Juan L. Aragón, José González, Antonio González:
Power-Aware Control Speculation through Selective Throttling. HPCA 2003: 103-112 - [c24]José González, Antonio González:
Dynamic Cluster Resizing. ICCD 2003: 375- - [c23]Gregorio Bernabé, José M. García, José González:
Reducing 3D Wavelet Transform Execution Time through the Streaming SIMD Extensions. PDP 2003: 49-56 - [c22]Javier Cuenca, Domingo Giménez, José González, Jack J. Dongarra, Kenneth Roche:
Automatic Optimisation of Parallel Linear Algebra Routines in Systems with Variable Load. PDP 2003: 409-416 - [c21]Javier Cuenca, Luis-Pedro García, Domingo Giménez, José González, Antonio M. Vidal:
Empirical Modelling of Parallel Linear Algebra Routines. PPAM 2003: 169-174 - 2002
- [c20]Manuel E. Acacio, José González, José M. García, José Duato:
The Use of Prediction for Accelerating Upgrade Misses in cc-NUMA Multiprocessors. IEEE PACT 2002: 155-164 - [c19]Gregorio Bernabé, José González, José M. García, José Duato:
Memory Conscious 3D Wavelet Transform. EUROMICRO 2002: 108-113 - [c18]Juan L. Aragón, José González, Antonio González, James E. Smith:
Dual path instruction processing. ICS 2002: 220-229 - [c17]Manuel E. Acacio, José González, José M. García, José Duato:
A Novel Approach to Reduce L2 Miss Latency in Shared-Memory Multiprocessors. IPDPS 2002 - [c16]Javier Cuenca, Domingo Giménez, José González:
Towards the Design of an Automatically Tuned Linear Algebra Library. PDP 2002: 201- - [c15]Manuel E. Acacio, José González, José M. García, José Duato:
Reducing the Latency of L2 Misses in Shared-Memory Multiprocessors through On-Chip Directory Integration. PDP 2002: 368-375 - [c14]Manuel E. Acacio, José González, José M. García, José Duato:
Owner prediction for accelerating cache-to-cache transfer misses in a cc-NUMA architecture. SC 2002: 1:1-1:12 - 2001
- [j3]José González, Antonio González:
Control-Flow Speculation through Value Prediction. IEEE Trans. Computers 50(12): 1362-1376 (2001) - [c13]Juan L. Aragón, José González, José M. García, Antonio González:
Confidence Estimation for Branch Prediction Reversal. HiPC 2001: 214-223 - [c12]Manuel E. Acacio, José González, José M. García, José Duato:
A New Scalable Directory Architecture for Large-Scale Multiprocessors. HPCA 2001: 97-106 - [c11]Juan L. Aragón, José González, José M. García, Antonio González:
Selective Branch Prediction Reversal By Correlating with Data Values and Control Flow. ICCD 2001: 228-233 - [c10]Javier Cuenca, Domingo Giménez, José González:
Modeling the Behaviour of Linear Algebra Algorithms with Message-Passing. PDP 2001: 282-289 - 2000
- [j2]Teresa Monreal, Antonio González, Mateo Valero, José González, Víctor Viñals:
Dynamic Register Renaming Through Virtual-Physical Registers. J. Instr. Level Parallelism 2 (2000)
1990 – 1999
- 1999
- [c9]José González, Antonio González:
Control-Flow Speculation through Value Prediction for Superscalar Processors. IEEE PACT 1999: 57-65 - [c8]Teresa Monreal, Antonio González, Mateo Valero, José González, Víctor Viñals:
Delaying Physical Register Allocation through Virtual-Physical Registers. MICRO 1999: 186-192 - 1998
- [j1]José González, Antonio González:
Data value speculation in superscalar processors. Microprocess. Microsystems 22(6): 293-301 (1998) - [c7]Antonio González, José González, Mateo Valero:
Virtual-Physical Registers. HPCA 1998: 175-184 - [c6]José González, Antonio González:
The Potential of Data Value Speculation to Boost ILP. International Conference on Supercomputing 1998: 21-28 - [c5]José González, Antonio González:
Limits of Instruction Level Parallelism with Data Value Speculation. VECPAR 1998: 452-465 - 1997
- [c4]José González, Antonio González:
Memory Address Prediction for Data Speculation. Euro-Par 1997: 1084-1091 - [c3]Antonio González, Mateo Valero, José González, Teresa Monreal Arnal:
Virtual registers. HiPC 1997: 364-369 - [c2]José González, Antonio González:
Speculative Execution via Address Prediction and Data Prefetching. International Conference on Supercomputing 1997: 196-203 - [c1]Nigel P. Topham, Antonio González, José González:
The Design and Performance of a Conflict-Avoiding Cache. MICRO 1997: 71-80
Coauthor Index
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