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ORCIDICCD 2003: San Jose, CA, USA
- 21st International Conference on Computer Design (ICCD 2003),VLSI in Computers and Processors, 13-15 October 2003, San Jose, CA, USA, Proceedings. IEEE Computer Society 2003, ISBN 0-7695-2025-1
Keynotes
- Mark Horowitz:
High-Speed Link Design, Then and Now. - William R. Pulleyblank:
Terascale Computing and BlueGene. - Ted Vucurevich:
Advanced EDA Tools for High-Performance Design.
Energy Efficiency
- Aneesh Aggarwal, Manoj Franklin:
Energy Efficient Asymmetrically Ported Register Files. 2-7 - Jaume Abella, Antonio González
:
Power Efficient Data Cache Designs. 8-13 - Jaume Abella, Antonio González:
On Reducing Register Pressure and Energy in Multiple-Banked Register Files. 14-20 - Masayuki Ito, David G. Chinnery, Kurt Keutzer:
Low Power Multiplication Algorithm for Switching Activity Reduction through Operand Decomposition. 21-
Timing Verification
- Hao Zheng, Chris J. Myers, David Walter, Scott Little, Tomohiro Yoneda:
Verification of Timed Circuits with Failure Directed Abstractions. 28-35 - Gang Chen, Sudhakar M. Reddy, Irith Pomeranz:
Procedures for Identifying Untestable and Redundant Transition Faults in Synchronous Sequential Circuits. 36-41 - Marong Phadoongsidhi, Kewal K. Saluja:
Event-Centric Simulation of Crosstalk Pulse Faults in Sequential Circuits. 42-47 - Edmund M. Clarke, Daniel Kroening, Karen Yorav:
Specifying and Verifying Systems with Multiple Clocks. 48-
Electrical Analysis for System LSI
- Wenjian Yu, Zeyi Wang, Xianlong Hong:
Enhanced QMM-BEM Solver for 3-D Finite-Domain Capacitance Extraction with Multilayered Dielectrics. 58-63 - Chih-Liang Huang, Aurobindo Dasgupta:
An Improved method for Fast Noise Estimation based on Net Segmentation. 64-79 - Hui-Yuan Song, S. Bohidar, R. Iris Bahar, Joel Grodstein:
Symbolic Failure Analysis of Custom Circuits due to Excessive Leakage Current. 70-75 - Venkatesan Rajappan, Sachin S. Sapatnekar:
An Efficient Algorithm for Calculating the Worst-case Delay due to Crosstalk. 76-
Power Optimization
- Payman Zarkesh-Ha, Ken Doniger, William Loh, Dechang Sun, Rick Stephani, Gordon Priebe:
A Compact Model for Analysis and Design of On-chip Power Network with Decoupling Capacitors. 84-89 - Afshin Abdollahi, Massoud Pedram, Farzan Fallah, Indradeep Ghosh:
Precomputation-based Guarding for Dynamic and Leakage Power Reduction. 90-97 - Saravanan Rajapandian, Zheng Xu, Kenneth L. Shepard:
Charge-Recycling Voltage Domains for Energy-Efficient Low-Voltage Operation of Digital CMOS Circuits. 98-102 - Hiroaki Suzuki, Woopyo Jeong, Kaushik Roy:
Low Power Adder with Adaptive Supply Voltage. 103-106 - Nestoras Tzartzanis, William W. Walker:
A Transparent Voltage Conversion Method and Its Application to a Dual-Supply-Voltage Register File. 107-
Gene Chip Design
- Rastislav Levicky:
Detection of Biological Molecules: From Self-Assembled Films to Self-Integrated Devices. 112-
Embedded Tutorial
- Andrew B. Kahng, Ion I. Mandoiu, Sherief Reda, Xu Xu, Alexander Zelikovsky:
Design Flow Enhancements for DNA Arrays. 116-
System Level Design
- Nattawut Thepayasuwan, Vaishali Damle, Alex Doboli:
Bus Architecture Synthesis for Hardware-Software Co-Design of Deep Submicron Systems on Chip. 126-133 - Vikas Chandra, Gary D. Carpenter, Jeffrey L. Burns:
Dynamically Optimized Synchronous Communication for Low Power System on Chip Designs. 134-139 - Manev Luthra, Sumit Gupta, Nikil D. Dutt, Rajesh K. Gupta, Alexandru Nicolau:
Interface Synthesis using Memory Mapping for an FPGA Platform. 140-145 - Alessandro Pinto, Luca P. Carloni, Alberto L. Sangiovanni-Vincentelli:
Efficient Synthesis of Networks On Chip. 146-150 - Mehrdad Reshadi, Nikil D. Dutt:
Reducing Compilation Time Overhead in Compiled Simulators. 151-
Systems Performance
- Branden J. Moore, Thomas Slabach, Lambert Schaelicke:
Profiling Interrupt Handler Performance through Kernel Instrumentation. 156-163 - Krishna Kant, Ravishankar K. Iyer:
Design and Performance of Compressed Interconnects for High Performance Servers. 164-169 - Karthikeyan Sankaralingam, Vincent Ajay Singh, Stephen W. Keckler, Doug Burger:
Routed Inter-ALU Networks for ILP Scalability and Performance. 170-
Micro Processor Test & Diagnosis
- Joel Grodstein, Dilip K. Bhavsar, Vijay Bettada, Richard A. Davies:
Automatic Generation of Critical-Path Tests for a Partial-Scan Microprocessor. 180-186 - Loganathan Lingappan, Srivaths Ravi, Niraj K. Jha:
Test Generation for Non-separable RTL Controller-datapath Circuits using a Satisfiability based Approach. 187-193 - Sobeeh Almukhaizim, Thomas Verdel, Yiorgos Makris:
Cost-Effective Graceful Degradation in Speculative Processor Subsystems: The Branch Prediction Case. 194-197 - Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski:
Multiple Fault Diagnosis Using n-Detection Tests. 198-
Physical Design
- Noriyuki Ito, Hiroaki Komatsu, Yoshiyasu Tanamura, Ryoichi Yamashita, Hiroyuki Sugiyama, Yaroku Sugiyama, Hirofumi Hamamura:
A Physical Design Methodology for 1.3GHz SPARC64 Microprocessor. 204-210 - Yangdong Deng, Wojciech Maly:
Physical Design of the "2.5D" Stacked System. 211-217 - Bo-Kyung Choi, Huaiyu Xu, Maogang Wang, Majid Sarrafzadeh:
Flow-Based Cell Moving Algorithm for Desired Cell Distribution. 218-
Performance Optimization
- Byeong Kil Lee, Lizy Kurian John:
NpBench: A Benchmark Suite for Control plane and Data plane Applications for Network Processors. 226-233 - Nihar R. Mahapatra, Jiangjiang Liu, Krishnan Sundaresan:
Hardware-Only Compression of Underutilized Address Buses: Design and Performance, Power, and Cost Analysis. 234-239 - Guy Even, Peter-Michael Seidel:
Pipelined Multiplicative Division with IEEE Rounding. 240-
Clock & Signal Distribution
- Steven C. Chan, Kenneth L. Shepard, Phillip J. Restle:
Design of Resonant Global Clock Distributions. 248-253 - Ganesh Balamurugan, Naresh R. Shanbhag:
Modeling and Mitigation of Jitter in Multi-Gbps Source-Synchronous I/O Links. 254-260 - Daniel Eckerbert, Lars J. Svensson, Per Larsson-Edefors:
A Mixed-Mode Delay-Locked-Loop Architecture. 261-263 - Shidhartha Das, Kanak Agarwal, David T. Blaauw, Dennis Sylvester:
Optimal Inductance for On-chip RLC Interconnections. 264-
Performance and Power-Driven Physical Design
- Nataraj Akkiraju, Mosur Mohan:
Spec Based Flip-Flop And Buffer Insertion. 270-275 - N. Ranganathan, Ashok K. Murugavel:
A Microeconomic Model for Simultaneous Gate Sizing and Voltage Scaling for Power Optimization. 276-281 - Rishi Chaturvedi, Jiang Hu:
A Simple Yet Effective Merging Scheme for Prescribed-Skew Clock Routing. 282-
Instruction Execution
- Shih-Chang Lai, Shih-Lien Lu:
Hardware-based Pointer Data Prefetcher. 290-298 - Sriram Nadathur, Akhilesh Tyagi:
A Dependence Driven Efficient Dispatch Scheme. 299-306 - Tay-Jyi Lin, Chin-Chi Chang, Chen-Chia Lee, Chein-Wei Jen:
An Efficient VLIW DSP Architecture for Baseband Processing. 307-312 - Mohamed M. Zahran, Manoj Franklin:
Dynamic Thread Resizing for Speculative Multithreaded Processors. 313-
Test Compression Technology
- Bernd Könemann:
Care Bit Density and Test Cube Clusters: Multi-Level Compression Opportunities. 320- - Subhasish Mitra, Kee Sup Kim:
XMAX: X-Tolerant Architecture for MAXimal Test Compression. 326-330 - Janusz Rajski, Jerzy Tyszer:
Test Data Compression and Compaction for Embedded Test of Nanometer Technology Designs. 331-
Physical Design for Regular Fabrics and FPGA's
- Aiqun Cao, Cheng-Kok Koh:
Non-Crossing OBDDs for Mapping to Regular Circuit Structures. 338-343 - PariVallal Kannan, Dinesh Bhatia:
Interconnect Estimation for FPGAs under Timing Driven Domains. 344-349 - Hasan Arslan, Shantanu Dutt:
ROAD : An Order-Impervious Optimal Detailed Router for FPGAs. 350-
Array Design Optimization
- Victor Delaluz, Mahmut T. Kandemir, Anand Sivasubramaniam, Mary Jane Irwin, Narayanan Vijaykrishnan:
Reducing dTLB Energy Through Dynamic Resizing. 358-363 - Gurhan Kucuk, Oguz Ergin, Dmitry Ponomarev, Kanad Ghose:
Distributed Reorder Buffer Schemes for Low Power. 364-370 - Peter Petrov, Alex Orailoglu:
Virtual Page Tag Reduction for Low-power TLBs. 371-374 - José González, Antonio González:
Dynamic Cluster Resizing. 375-
Test Compaction
- Petros Drineas, Yiorgos Makris:
Independent Test Sequence Compaction through Integer Programming. 380-386 - Seiji Kajihara, Yasumi Doi, Lei Li, Krishnendu Chakrabarty:
On Combining Pinpoint Test Set Relaxation and Run-Length Codes for Reducing Test Data Volume. 387-396 - Irith Pomeranz, Sudhakar M. Reddy:
Static Test Compaction for Multiple Full-Scan Circuits. 393-396 - Yoshinobu Higami, Shin-ya Kobayashi, Yuzo Takamatsu, Seiji Kajihara, Irith Pomeranz:
A Method to Find Don't Care Values in Test Sequences for Sequential Circuits. 397-
Techniques for Synthesizing into Fabrics
- C. Ross Ogilvie, Richard Ray, Robert Devins, Mark Kautzman, Michael Hale, Reinaldo A. Bergamaschi, Bob Lynch, Santosh Gaur:
Simplifying SoC design with the Customizable Control Processor Platform. 402-403 - Behrooz Zahiri:
Structured ASICs: Opportunities and Challenges. 404-409 - Sinan Kaptanoglu:
System LSI Implementation Fabrics for the Future (special panel discussion). 410-
Hardware Partitioning
- Dongku Kang, Mark C. Johnson, Kaushik Roy:
Multiple-Vdd Scheduling/Allocation for Partitioned Floorplan. 412-418 - Young-Su Kwon, Bong-Il Park, Chong-Min Kyung:
SCATOMi: Scheduling Driven Circuit Partitioning Algorithm for Multiple FPGAs using Time-multiplexed, Off-chip, Multicasting Interconnection Architecture. 419-425 - Kaushal R. Gandhi, Nihar R. Mahapatra:
A Study of Hardware Techniques That Dynamically Exploit Frequent Operands to Reduce Power Consumption in Integer Function Units. 426-
Energy-Aware Design and Application
- Chandramouli Gopalakrishnan, Srinivas Katkoori:
KnapBind: An Area-Efficient Binding Algorithm for Low-leakage Datapaths. 430-435 - Madhubanti Mukherjee, Ranga Vemuri:
A Novel Synthesis Strategy Driven by Partial Evaluation Based Circuit Reduction for Application Specific DSP Circuits. 436-440 - Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi:
Power Fluctuation Minimization During Behavioral Synthesis using ILP-Based Datapath Scheduling. 441-443 - Farhad Ghasemi-Tari, Peng Rong, Massoud Pedram:
An Energy-Aware Simulation Model and Transaction Protocol for Dynamic Workload Distribution in Mobile Ad Hoc Networks. 444-
High-Speed Design Issues and Test Challenges
- Ming-Ju Edward Lee, William J. Dally, Ramin Farjad-Rad, Hiok-Tiaq Ng, Ramesh Senthinathan, John H. Edmondson, John W. Poulton:
CMOS High-Speed I/Os - Present and Future. 454-461 - Kursad Kiziloglu, Shivakumar Seetharaman, K. W. Glass, C. Bil, H. V. Duong, G. Asmanis:
Fully Differential Receiver Chipset for 40 Gb/s Applications Using GaInAs/InP Single Heterojunction Bipolar Transistors. 462-466 - Mike Peng Li, Jan B. Wilstrup:
Paradigm Shift For Jitter and Noise In Design and Test > GB/s Communication Systems. 467-
Efficiency and Reliability
- Chanik Park, Jaeyu Seo, Dongyoung Seo, Shinhan Kim, Bumsoo Kim:
Cost-Efficient Memory Architecture Design of NAND Flash Memory Embedded Systems. 474-480 - Premkishore Shivakumar, Stephen W. Keckler, Charles R. Moore, Doug Burger:
Exploiting Microarchitectural Redundancy For Defect Tolerance. 481-488 - Zhijian Lu, John C. Lach, Mircea R. Stan, Kevin Skadron:
Reducing Multimedia Decode Power using Feedback Control. 489-
Novel Methods in Logic Synthesis
- Guoqiang Wang, Andreas Kuehlmann, Alberto L. Sangiovanni-Vincentelli:
Structural Detection of Symmetries in Boolean Functions. 498-503 - Elena Dubrova, Maxim Teslenko, Johan Karlsson:
Boolean Decomposition Based on Cyclic Chains. 504-509 - Samir Sapra, Michael Theobald, Edmund M. Clarke:
SAT-Based Algorithms for Logic Minimization. 510-
Communications and Context Management
- Anand Selvarathinam, Euncheol Kim, Gwan Choi:
Low-Density Parity-Check Decoder Architecture for High Throughput Optical Fiber Channels. 520-525 - Sudeep Pasricha, Alexander V. Veidenbaum:
Improving Branch Prediction Accuracy in Embedded Processors in the Presence of Context Switches. 526-531 - Santithorn Bunchua, D. Scott Wills, Linda M. Wills:
Reducing Operand Transport Complexity of Superscalar Processors using Distributed Register Files. 532-535 - Matteo Dall'Osso, Gianluca Biccari, Luca Giovannini, Davide Bertozzi, Luca Benini:
xpipes: a Latency Insensitive Parameterized Network-on-chip Architecture For Multi-Processor SoCs. 536-
Board Test and Power-Aware Test
- Ozgur Sinanoglu, Alex Orailoglu:
Aggressive Test Power Reduction Through Test Stimuli Transformation. 542-547 - Mehrdad Nourani, James Chin:
Power-Time Tradeoff in Test Scheduling for SoCs. 548-553 - Mohammad H. Tehranipour, Nisar Ahmed, Mehrdad Nourani:
Multiple Transition Model and Enhanced Boundary Scan Architecture to Test Interconnects for Signal Integrity. 554-
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