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Antonio Sanchez-Clemente
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2020 – today
- 2024
- [j3]Yubal Barrios
, Joan Bartrina-Rapesta
, Miguel Hernández-Cabronero
, Antonio Sanchez-Clemente
, Ian Blanes
, Joan Serra-Sagristà
, Roberto Sarmiento
:
Removing Data Dependencies in the CCSDS 123.0-B-2 Predictor Weight Updating. IEEE Geosci. Remote. Sens. Lett. 21: 1-5 (2024) - 2023
- [j2]Luis Entrena
, Antonio J. Sanchez-Clemente
, Luis Ángel García-Astudillo
, Marta Portela-García, Mario García-Valderas
, Almudena Lindoso
, Roberto Sarmiento
:
Formal Verification of Fault-Tolerant Hardware Designs. IEEE Access 11: 116127-116140 (2023)
2010 – 2019
- 2018
- [c4]Antonio Sanchez-Clemente, Luis Entrena
, Fernanda Lima Kastensmidt:
Approximate TMR for selective error mitigation in FPGAs based on testability analysis. AHS 2018: 112-119 - [c3]Iuri Albandes Cunha Gomes, Alejandro Serrano-Cases
, Antonio J. Sanchez-Clemente, Mayler G. A. Martins, Antonio Martínez-Álvarez
, Sergio Cuenca-Asensi
, Fernanda Lima Kastensmidt:
Improving approximate-TMR using multi-objective optimization genetic algorithm. LATS 2018: 1-6 - 2016
- [j1]Antonio Sanchez-Clemente, Luis Entrena
, Radek Hrbacek, Lukás Sekanina:
Error Mitigation Using Approximate Logic Circuits: A Comparison of Probabilistic and Evolutionary Approaches. IEEE Trans. Reliab. 65(4): 1871-1883 (2016) - 2014
- [c2]Antonio Sanchez-Clemente, Luis Entrena
, Mario García-Valderas
:
Error masking with approximate logic circuits using dynamic probability estimations. IOLTS 2014: 134-139 - 2012
- [c1]Antonio Sanchez-Clemente, Luis Entrena
, Mario García-Valderas
, Celia López-Ongil
:
Logic masking for SET Mitigation Using Approximate Logic Circuits. IOLTS 2012: 176-181
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last updated on 2024-04-25 05:58 CEST by the dblp team
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